F-Tile Dynamic Reconfiguration Design Example User Guide

ID 710582
Date 10/06/2023
Public
Document Table of Contents

1.7. Testing the Hardware Design Example

The F-Tile Dynamic Reconfiguration Design Example runs the external loopback test by default with the loopback_mode parameter set to 0. Before performing any hardware test, attach the QSFP-DD loopback module according to the QSF pinout assignments of the respective design example. To perform an internal loopback test in hardware, modify the loopback_mode parameter to 1 in the parameter.tcl file located in <design_example_dir>/hardware_test_design/hwtest/src. After you compile the F-Tile dynamic reconfiguration design example and configure it on your Intel Agilex® 7 device, you can use the System Console to program the IP core and its PHY IP core registers.

The hardware design example executes the dynamic reconfiguration transition process based on your selections as stated in <design_example_dir>/hardware_test_design/hwtest/src/parameter.tcl file and checks the DUT IP status. The dynamic reconfiguration transition sequence is set by default. However, you can always change it by modifying the DR_TRANSITION array variable in theparameter.tcl file to change the transition sequence.

DR_TRANSITION: Intended dynamic reconfiguration sequence array. The size of this array variable determines the number of dynamic reconfigurations to be performed.

To start the System Console and test the hardware design example, follow these steps:

  1. After the hardware design example is configured on the Intel Agilex® 7 device, in the Intel® Quartus® Prime Pro Edition software, click Tools > System Debugging Tools > System Console.
  2. In the Tcl Console pane, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest.
  3. Type source main_script.tcl to open a connection to the JTAG master and start the test.
  4. Analyze the results. Successful run displays Test Passed in the System Console.
    Note: If internal serial loopback (ILB) is enabled for the current profile, you need to disable it using the FGT attribute access method before performing dynamic reconfiguration to the next target profile. If you do not follow this, you might observe that the Quartus Hard IP performs abnormally after dynamic reconfiguration.

    The information in this section for testing the design example in hardware applies to the following dynamic reconfiguration design example: