F-Tile Dynamic Reconfiguration Design Example User Guide

ID 710582
Date 10/06/2023
Public
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1.5. Simulating the Design Example Testbench

Procedure

Follow these steps to simulate the testbench:

  1. At the command prompt, change to the testbench simulation directory <design_example_dir>/example_testbench.
    cd <my_design>/example_testbench
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
  3. Analyze the results. The successful simulation displays "Testbench Passed" or "Test Case Passed" message.
    Table 8.  Steps to Simulate the Testbench in Synopsys VCS* Simulator
    Simulator Instructions
    VCS* In the command line, type:
    sh run_vcs.sh
    Note: Dynamic Reconfiguration with AN/LT IP supports only VCS simulators in design example.
    VCS* MX In the command line, type:
    sh run_vcsmx.sh
    QuestaSim* In the command line, type:
    vsim -do run_vsim.do
    If you prefer to simulate without bringing up the GUI, type:
    vsim -c -do run_vsim.do
    Xcelium* In the command line, type:
    sh run_xcelium.sh
    The following sample output illustrates a successful simulation test run for the CPRI multirate design example testbench.
    NIOS is entering reset
    NIOS is exiting reset
    basic_avl_tb_top.cpriphy_dr_ed_hw__tiles.z1577a_x0_y0_n0.z1577a.z1577a_inst.PROTECTED: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.
    SIM Mode Conversion TX AM PERIOD Standard Mode: 163832 Sim Mode:   2552
    ** Info: Configuring ED to CPRI 10G ....
    ** Info: Wait for DR Ready....
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Starting CPRI 10G....
    ** Address offset = 0x1, WriteData = 0x00000001
    ** Address offset = 0x2, WriteData = 0x00008006
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Trigger DR interrupt
    ** Address offset = 0x0, WriteData = 0x00000001
    ** Info: Wait for DR interrupt Ack....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: Wait for DR Config to be done....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: DONE Reconfigure to CPRI 10G ....
    ** Address offset = 0x0, WriteData = 0x00000009
    ** Address offset = 0x1, WriteData = 0x00000009
    ** Info: De-asserting reset to CPRI ....
    Waiting for TX ready
    TX is ready is high at time             689130000
    Waiting for RX ready
    RX is ready is high at time             709850000
    *** sending packets in progress, waiting for checker pass ***
    ** Channel 0: RX checker has received packets correctly!
    ** PASSED
    ** Info: Configuring ED to CPRI 9p8G ....
    ** Info: Wait for DR Ready....
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Starting CPRI 9p8G....
    ** Address offset = 0x1, WriteData = 0x00000006
    ** Address offset = 0x2, WriteData = 0x00008007
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Trigger DR interrupt
    ** Address offset = 0x0, WriteData = 0x00000001
    ** Info: Wait for DR interrupt Ack....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: Wait for DR Config to be done....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: DONE Reconfigure to CPRI 9p8G ....
    ** Address offset = 0x0, WriteData = 0x00000006
    ** Address offset = 0x1, WriteData = 0x00000006
    ** Info: De-asserting reset to CPRI ....
    Waiting for TX ready
    TX is ready is high at time            1561660000
    Waiting for RX ready
    RX is ready is high at time            1579800000
    *** sending packets in progress, waiting for checker pass ***
    ** Channel 0: RX checker has received packets correctly!
    ** PASSED
    ** Info: Configuring ED to CPRI 4p9G ....
    ** Info: Wait for DR Ready....
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Starting CPRI 4p9G....
    ** Address offset = 0x1, WriteData = 0x00000007
    ** Address offset = 0x2, WriteData = 0x00008009
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Trigger DR interrupt
    ** Address offset = 0x0, WriteData = 0x00000001
    ** Info: Wait for DR interrupt Ack....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: Wait for DR Config to be done....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: DONE Reconfigure to CPRI 4p9G ....
    ** Address offset = 0x0, WriteData = 0x00000004
    ** Address offset = 0x1, WriteData = 0x00000004
    ** Info: De-asserting reset to CPRI ....
    Waiting for TX ready
    TX is ready is high at time            2415120000
    Waiting for RX ready
    RX is ready is high at time            2433780000
    *** sending packets in progress, waiting for checker pass ***
    ** Channel 0: RX checker has received packets correctly!
    ** PASSED
    ** Info: Configuring ED to CPRI 2p4G ....
    ** Info: Wait for DR Ready....
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Starting CPRI 2p4G....
    ** Address offset = 0x1, WriteData = 0x00000009
    ** Address offset = 0x2, WriteData = 0x0000800b
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Trigger DR interrupt
    ** Address offset = 0x0, WriteData = 0x00000001
    ** Info: Wait for DR interrupt Ack....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: Wait for DR Config to be done....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: DONE Reconfigure to CPRI 2p4G ....
    ** Address offset = 0x0, WriteData = 0x00000002
    ** Address offset = 0x1, WriteData = 0x00000002
    ** Info: De-asserting reset to CPRI ....
    Waiting for TX ready
    TX is ready is high at time            3269140000
    Waiting for RX ready
    RX is ready is high at time            3287790000
    *** sending packets in progress, waiting for checker pass ***
    ** Channel 0: RX checker has received packets correctly!
    ** PASSED
    ** Info: Configuring ED to CPRI 24p3G_RSFEC ....
    ** Info: Wait for DR Ready....
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Starting CPRI 24p3G_RSFEC....
    ** Address offset = 0x1, WriteData = 0x0000000b
    ** Address offset = 0x2, WriteData = 0x00008001
    ** Address offset = 0x0, ReadData  = 0x00000002
    ** Info: Trigger DR interrupt
    ** Address offset = 0x0, WriteData = 0x00000001
    ** Info: Wait for DR interrupt Ack....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: Wait for DR Config to be done....
    ** Address offset = 0x0, ReadData  = 0x00000000
    ** Info: DONE Reconfigure to CPRI 24p3G_RSFEC ....
    ** Address offset = 0x0, WriteData = 0x0000001b
    ** Address offset = 0x1, WriteData = 0x0000001b
    ** Info: De-asserting reset to CPRI ....
    Waiting for TX ready
    TX is ready is high at time            4158420000
    Waiting for RX ready
    RX is ready is high at time            4196310000
    *** sending packets in progress, waiting for checker pass ***
    ** Channel 0: RX checker has received packets correctly!
    ** PASSED
    ** Testbench Completed
    ** Testbench Passed
    $finish called from file "basic_avl_tb_top.sv", line 452.
    $finish at simulation time 4196335ns
    
    The following sample output illustrates a successful simulation test run for the 100G-4 Ethernet multirate dynamic reconfiguration IP core variant.
    ---SRC IP sequence TX ch0 completed ----
    ---SRC IP sequence TX ch1 completed ----
    
    ---SRC IP sequence RX ch0 completed ----
    ---SRC IP sequence RX ch1 completed ----
    
    ---Test 50G ch 0;   ---Total 16 packets to send ----
    Clearing counters
    -----Start 50G pkt gen TX ----
    -----Checking 50G Packet TX/RX result ----
    ---------- 16 packets Sent; 0 packets Received ----
    ------ALL 16 packets Sent out ---
    
    ---------- 16 packets Sent; 16 packets Received ----
    ------ALL 16 packets Received ---
    ------50G TX/RX packet check OK ---
    
    ---Test 50G ch 1;   ---Total 32 packets to send ----
    Clearing counters
    -----Start 50G pkt gen TX ----
    -----Checking 50G Packet TX/RX result ----
    ---------- 16 packets Sent; 0 packets Received ----
    ---------- 32 packets Sent; 32 packets Received ----
    ------ALL 32 packets Sent out ---
    ------ALL 32 packets Received ---
    ------50G TX/RX packet check OK ---
    
    *******************************************
    ** Testbench complete
    ** Testbench Passed
    **
    *******************************************
    The following sample output illustrates a successful simulation test run for the 50G-1 PMA/FEC Direct PHY Multirate design example testbench.
    ** Info: DONE Reconfigure to PMA DIR 50G ....
    ####### tx_reset, rx_reset deasserted ######
    1.08923e+09
    The time now is 1090000ns 
    
    The time now is 1100000ns 
    
    @1106614ns: TX Ready=0, RX Ready=0, verifier_error=0, verifier_lock =0, ux_locked =0, cdr_lockedtoref =1, cdr_locktodata= 0, fnl_xcvr_locked_dut = 0,  tx_clkout_freq_valid=0, rx_clkout_freq_valid=0
    The time now is 1110000ns 
    
    @1110766ns: TX Ready=0, RX Ready=0, verifier_error=0, verifier_lock =0, ux_locked =1, cdr_lockedtoref =1, cdr_locktodata= 0, fnl_xcvr_locked_dut = 0,  tx_clkout_freq_valid=0, rx_clkout_freq_valid=0
    The time now is 1120000ns 
    
    @1126396ns: TX Ready=1, RX Ready=0, verifier_error=0, verifier_lock =0, ux_locked =1, cdr_lockedtoref =1, cdr_locktodata= 0, fnl_xcvr_locked_dut = 0,  tx_clkout_freq_valid=0, rx_clkout_freq_valid=0
    @1127420ns: TX Ready=1, RX Ready=0, verifier_error=0, verifier_lock =0, ux_locked =1, cdr_lockedtoref =1, cdr_locktodata= 0, fnl_xcvr_locked_dut = 0,  tx_clkout_freq_valid=1, rx_clkout_freq_valid=0
    @1128074ns: TX Ready=1, RX Ready=0, verifier_error=0, verifier_lock =0, ux_locked =1, cdr_lockedtoref =1, cdr_locktodata= 1, fnl_xcvr_locked_dut = 1,  tx_clkout_freq_valid=1, rx_clkout_freq_valid=0
    The time now is 1130000ns 
    
    The time now is 1140000ns 
    
    @1144500ns: TX Ready=1, RX Ready=1, verifier_error=0, verifier_lock =0, ux_locked =1, cdr_lockedtoref =1, cdr_locktodata= 1, fnl_xcvr_locked_dut = 1,  tx_clkout_freq_valid=1, rx_clkout_freq_valid=0
    @1144815ns: TX Ready=1, RX Ready=1, verifier_error=0, verifier_lock =1, ux_locked =1, cdr_lockedtoref =1, cdr_locktodata= 1, fnl_xcvr_locked_dut = 1,  tx_clkout_freq_valid=1, rx_clkout_freq_valid=0
    @1145521ns: TX Ready=1, RX Ready=1, verifier_error=0, verifier_lock =1, ux_locked =1, cdr_lockedtoref =1, cdr_locktodata= 1, fnl_xcvr_locked_dut = 1,  tx_clkout_freq_valid=1, rx_clkout_freq_valid=1
    test_pass asserted at 1148815ns
    
    Test case passed
    Overall DR test passed
    Simulation passed

    The following sample output illustrates a successful simulation test run for the Ethernet to CPRI design example testbench.

    The time now is 630000ns
    
    The time now is 6400000ns
    
    The time now is 650000ns
    
    The time now is 660000ns
    
    The time now is 670000ns
    
    The time now is 680000ns
    
    ** Info: Starting CPRI4.9G configuration....
    ** Info: Trigger DR interrupt
    ** Info: Wait for DR interrupt Ack....
    ** Info: Wait for DR Config to be done....
    The time now is 690000ns 
    
    The time now is 700000ns
    
    The time now is 710000ns
    
    The time now is 720000ns
    
    The time now is 730000ns
    
    The time now is 740000ns
    
    ** Info: Program DUT soft CSR ....
    The time now is 750000ns 
    
    ** Info: DONE Reconfigure to CPRI 4.9G....
    ** Info: De-asserting reset to CPRI ....
    ---SRC IP sequence started -----
    Waiting for TX ready
    The time now is 760000ns 
    
    The time now is 770000ns 
    
    TX is ready is high at time             777412533
    Waiting for RX ready
    The time now is 780000ns 
    
    The time now is 790000ns 
    
    RX is ready is high at time             794088533
    *** sending packets in progress, waiting for checker pass ***
    ** Channel 0: RX checker has received packets correctly!
    ** PASSED
    **
    *****************************************
    ** Testbench complete
    ** Testbench Passed
    **
    *****************************************
    $finish called from file "basic_avl_tb_top.sv", line 2251.