F-Tile Dynamic Reconfiguration Design Example User Guide

ID 710582
Date 10/06/2023
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5.2. PMA/FEC Direct PHY Multirate Design Example: Registers

Table 16.  Address Map for 50G-1 Base Variant
Address Range (Byte Addressing) Maps to
0x00000000 - 0x0001FFFF F-Tile PMA/FEC Direct PHY Intel® FPGA IP Soft CSR Registers and F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Reconfiguration Soft CSR Registers.
Note: For F-Tile PMA/FEC Direct PHY Soft CSR registers, refer to F-Tile PMA/FEC Direct PHY Intel FPGA IP Register Map. The register addresses in the reference document use byte addressing format instead of word addressing format.
Note: For F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Reconfiguration Soft CSR Registers, refer to F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP User Guide; Soft CSR Registers.
0x00800000 - 0x008FFFFF FGT and FHT PMA Registers
0x10000000 - 0x100003FF Dynamic Reconfiguration Controller Registers.
Note: For a complete list and detailed information about the Dynamic Reconfiguration control and status registers, refer to the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP User Guide; Configuration Registers.
Table 17.  Address Map for 400G-8 Base Variant
Address Range (Byte Addressing) Maps to
0x00000000 - 0x000FFFFF F-Tile PMA/FEC Direct PHY Intel® FPGA IP Soft CSR Registers and F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Reconfiguration Soft CSR Registers.
Note: For F-Tile PMA/FEC Direct PHY Soft CSR registers, refer to F-Tile PMA/FEC Direct PHY Intel FPGA IP Register Map. The register addresses in the reference document use byte addressing format instead of word addressing format.
Note: For F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Reconfiguration Soft CSR Registers, refer to F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP User Guide; Soft CSR Registers.
0x04000000 - 0x047FFFFF FGT and FHT PMA Registers
0x10000000 - 0x100003FF Dynamic Reconfiguration Controller Registers.
Note: For a complete list and detailed information about the Dynamic Reconfiguration control and status registers, refer to the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP User Guide; Configuration Registers.