F-Tile Dynamic Reconfiguration Design Example User Guide

ID 710582
Date 10/06/2023
Public
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1.6. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Intel Agilex® 7 device, follow these steps:

  1. Ensure that hardware design example generation is complete.
  2. In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project:
    • For CPRI Multirate Design Example:

      <design_example_dir>/hardware_test_design/cpriphy_dr_ed_hw.qpf

    • For Ethernet Multirate Design Example: <design_example_dir>/hardware_test_design/eth_f_hw.qpf
    • For PMA/FEC Direct PHY Multirate Design Example: <design_example_dir>/hardware_test_design/dphy_f_hw.qpf
    • For Ethernet to CPRI Design Example: <design_example_dir>/hardware_test_design/eth_cpriphy_f_hw.qpf
  3. Click Processing > Start Compilation.
  4. After successful compilation, a .sof file is available in <design_example_dir>/hardware_test_design/output_files directory. Follow these steps to program the hardware design example on the Intel Agilex® 7 device:
    1. Connect the Intel Agilex® 7 I-series Transceiver Signal Integrity Development Kit to the host computer.
      Note: The development kit is preprogrammed with the correct clock frequencies by default. You do not need to use the Clock Control application to set the frequencies.
    2. Click Tools > Programmer > Hardware Setup.
    3. Select a programming device.
    4. Ensure that Mode is set to JTAG.
    5. Select the Intel Agilex® 7 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    6. In the row with your .sof, check the box for the .sof.
    7. Check the box in the Program/Configure column.
    8. Click Start.