F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example 5. Detailed Description for Ethernet to CPRI Design Example 6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
3.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 3.2. PMA/FEC Direct PHY Multirate Design Example: Registers
3.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
3.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 3.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example
4. Detailed Description for Ethernet Multirate Design Example x
4.1. Ethernet Multirate Design Example: Functional Description 4.2. Ethernet Multirate Design Example: Registers
4.1. Ethernet Multirate Design Example: Functional Description x
4.1.1. Ethernet Multirate Design Example: Simulation Testbench Dynamic Reconfiguration Sequence Example: 100GE-4 > 2x 50GE-1 > 4x 25GE-1 4.1.2. Ethernet Multirate Hardware Design Example
5. Detailed Description for Ethernet to CPRI Design Example x
5.1. Ethernet to CPRI Design Example: Functional Description 5.2. Ethernet to CPRI Design Example: Registers
5.1. Ethernet to CPRI Design Example: Functional Description x
5.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 5.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example
5. Detailed Description for Ethernet to CPRI Design Example
6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

4.1.1. Ethernet Multirate Design Example: Simulation Testbench

Figure 14. Simulation Testbench Block Diagram for 25GE-1 Base Variant
Figure 15. Simulation Testbench Block Diagram for 25GE-1 with PTP Base Variant
Figure 16. Simulation Testbench Block Diagram for 100GE-4 Base VariantThe packet client block is available for each of the Ethernet rates.
Figure 17. Simulation Testbench Block Diagram for 100GE-4 with PTP Base VariantThe packet client block is available for each of the Ethernet rates.
Figure 18. Simulation Testbench Block Diagram for 400GE-8 Base VariantThe packet client block is available for each of the Ethernet rates.
Figure 19. Simulation Testbench Block Diagram for 400GE-8 with PTP Base VariantThe packet client block is available for each of the Ethernet rates.
Figure 20. Simulation Testbench Block Diagram for 400G-4 FHT Base Variant

The testbench program controls the testbench components via Avalon® memory-mapped interface access, status and control signals. The Avalon® memory-mapped interface arbiter decodes the Avalon® memory-mapped interface access from testbench program into multiple Avalon® memory-mapped interface slaves.

Simulation Flow:
  • Ethernet Multirate IP DUT is power-up based on base profile.
  • Initialize the testbench variables based on power-up profile. The parameter settings, located in the basic_avl_tb_top.sv file, are:
    • DR_NUM: To indicate the number of dynamic reconfiguration transitions.
    • DR_SEQ: To indicate the dynamic reconfiguration sequence.
  • Perform dynamic reconfiguration.
  • Check the testbench error flag and determine whether testbench passed or failed. The error flag is set to 1 if there is any error after dynamic reconfiguration traffic tests.

For customization, you can modify the DR_NUM and DR_SEQ localparam to configure the test flow. The profile ID is passed to the IP to configure the intended dynamic reconfiguration task.

Dynamic Reconfiguration Sequence Example: 100GE-4 > 2x 50GE-1 > 4x 25GE-1

To achieve this dynamic reconfiguration sequence, you must perform two dynamic reconfiguration transitions and specify the reconfiguration sequence. You update the local parameter settings file: 
// Available Modes
localparam DR_MODE_1X100GE_4       = 6'b00_00_00;
localparam DR_MODE_1X100GE_4_NOFEC = 6'b00_00_01; 
localparam DR_MODE_1X100GE_2       = 6'b00_00_11;
localparam DR_MODE_2x50GE_1        = 6'b01_01_00;
localparam DR_MODE_4X25GE_1 	   = 6'b10_00_00;
localparam DR_MODE_4X25GE_1_NOFEC  = 6'b10_00_01;

// Dynamic Reconfiguration setting
localparam DR_NUM = 2;
localparam [6:0] DR_SEQ [DR_NUM - 1 : 0] = {DR_MODE_4X25GE_1, DR_MODE_2X50GE_1}
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