3.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example
In the hardware design example, the ISSP modules control the DUT IP reset signals, dr_mode selection and shows the status signals. The hardware test scripts open service to the ISSP to read and drive the values. A JTAG host is instantiated to access the Avalon® memory-mapped interface.
The hardware design example executes the dynamic reconfiguration transition process based on user selection as stated in src/parameter.tcl file and checks the DUT IP status. There is a default dynamic reconfiguration transition sequence, but user can always modify the DR_TRANSITION array variable in src/parameter.tcl file.
DR_TRANSITION: Intended DR sequence array, size of this array variable determines the number of dynamic reconfiguration to be performed.
- For example, if you want to achieve the following dynamic reconfiguration sequence for 50G-1 Base Variant: 1x50G > 1x25G > 1x50G KPFEC > 1x24.33024G > 1x50G, the variables changes are:
set DR_TRANSITION(0) "1x25G" set DR_TRANSITION(1) "1x50G KPFEC" set DR_TRANSITION(2) "1x24.33024G" set DR_TRANSITION(3) "1x50G
- If you want to achieve the following dynamic reconfiguration sequence for 400G-8 Base Variant: 1x400G-8 > 2x100G-4 > 2x200G-4 > 1x400G-8G, the variables changes are:
The variables changes are: set DR_TRANSITION(0) "2x100G_4" set DR_TRANSITION(1) "2x200G_4" set DR_TRANSITION(2) "1x400G_8"
Hardware Flow for Design Example:
The PMA/FEC Direct Multirate PHY Design Example runs the external loopback test by default with the loopback_mode parameter set to 0. Before performing any hardware test, attach the QSFP-DD loopback module according to the QSF pinout assignments of the respective design example.
To perform an internal loopback test in hardware, modify the loopback_mode parameter to 1 in the parameter.tcl file located in <design_example_dir>/hardware_test_design/hwtest/src. After you compile the F-Tile dynamic reconfiguration design example and configure it on your Intel® Agilex™ 7 device, you can use the System Console to program the IP core and its PHY IP core registers.
About this task:
To start the System Console and test the hardware design example, follow these steps:
- After the hardware design example is configured on the Intel® Agilex™ 7 device, in the Intel Quartus Prime Pro Edition software, click .
- In the Tcl Console pane, type cd hwtest to change directory to <design_example_dir>/hardware_test_design/hwtest.
- Type source main_script.tcl to open a connection to the JTAG master and start the test.
- Analyze the results. Successful run displays Test Passed in the System Console.
The sample output for the PMA/FEC Direct PHY Multirate hardware design examples is shown below.
% cd hwtest
$source main_script.tcl
Info: Number of Channels = 1
Info: JTAG Port ID = 2
Info: Power Up Variant = 1x50G
INFO: Start of ftile_dphy_dr_test_dynamic
INFO: Basic DPHY DR test
INFO: Set Reconfig Reset
INFO: write_value is 0x1
INFO: Release Reconfig Reset
INFO: write_value is 0x0
INFO: Set DR mode...
INFO: DR mode is 0x0
...........
*******
*******
INFO: Channel 0: Set TX Reset
INFO: write_value is 0x4
INFO: Channel 0: Set RX Reset
INFO: write_value is 0x6
INFO: get_reset_ack_status -----
INFO: Channel 0 : Checking tx reset ack status...
INFO: tx_reset_ack_status_0 = 0x3
INFO: TX fully in reset state
INFO: Channel 0 : Checking rx reset ack status...
INFO: rx_reset_ack_status_0 = 0x3
INFO: RX fully in reset state
INFO: Start DR selection-----
INFO: DR transition is 1x50G -----
INFO: Channel: 0 Configuring ED to PMA_DIR 1x50G ....
INFO: Wait for DR Ready....
INFO: configuring DR Profile 1x50G....
INFO: Trigger DR interrupt
INFO: Wait for DR interrupt Ack....
INFO: DR Request acknowledged
INFO: Wait for DR Config to be done....
INFO: DONE Reconfigure to 1x50G.
INFO: Set DR mode...
INFO: DR mode is 0x0
INFO: Channel 0: Release TX Reset
INFO: write_value is 0x2
INFO: Channel 0: Release RX Reset
INFO: write_value is 0x0
INFO: Channel 0 : Run test...
INFO: Read out probe data: 0x7dc
INFO: Data locked with no error
*******
*******
Info: End of ftile_dphy_dr_test
Info: Test <ftile_dphy_dr_test> Passed
% cd hwtest
$source main_script.tcl
Info: Number of Channels = 1
Info: JTAG Port ID = 2
Info: Power Up Variant = 1x400G_8
INFO: Start of ftile_dphy_dr_test
INFO: Basic DPHY DR test
INFO: Set Reconfig Reset
INFO: write_value is 0x1
INFO: Release Reconfig Reset
INFO: write_value is 0x0
INFO: Set DR mode...
INFO: DR mode is 0x0
INFO: Channel 0: Set TX Reset
INFO: write_value is 0x4
INFO: Channel 0: Set RX Reset
INFO: write_value is 0x6
INFO: check_reset_ack_n_status for current_dr_profile : 400G -----
INFO: Channel 0 : Checking tx reset ack status...
INFO: tx_reset_ack_status_0 = 0x5
INFO: TX fully in reset state
INFO: Channel 0 : Checking rx reset ack status...
INFO: rx_reset_ack_status_0 = 0x5
INFO: RX fully in reset state
INFO: Internal Serial Loopback not enabled
INFO: Channel 0: Release TX Reset
INFO: write_value is 0x2
INFO: Channel 0: Release RX Reset
INFO: write_value is 0x0
Run default test. Release resets. Running test for 10s
INFO: Channel 0 : Run test...
INFO: Read out probe data: 0x6b70
INFO: Channel 0: Set TX Reset
INFO: write_value is 0x4
INFO: Channel 0: Set RX Reset
INFO: write_value is 0x6
INFO: check_reset_ack_n_status for current_dr_profile : 400G -----
INFO: Channel 0 : Checking tx reset ack 0 status...
INFO: tx_reset_ack_status_0 = 0x5
INFO: TX fully in reset state
INFO: Channel 0 : Checking rx reset ack status...
INFO: rx_reset_ack_status_0 = 0x5
INFO: RX fully in reset state
INFO: Start DR selection-----
INFO: DR transition is 2x200G_4 -----
INFO: Channel: 0 Configuring ED to PMA_DIR 2x200G_4 ....
INFO: Wait for DR Ready....
INFO: configuring DR Profile 2x200G_4....
INFO: Trigger DR interrupt
INFO: Wait for DR interrupt Ack....
INFO: DR Request acknowledged
INFO: Wait for DR Config to be done....
INFO: DONE Reconfigure to 2x200G_4.
INFO: Set DR mode...
INFO: DR mode is 0x1
INFO: Channel 0: Release TX Reset
INFO: write_value is 0x2
INFO: Channel 0: Release RX Reset
INFO: write_value is 0x0
INFO: Channel 0 : Run test...
INFO: Read out probe data: 0x7f70
INFO: Data locked with no error
INFO: Test Pass!
*******
*******
INFO: Channel 0: Set TX Reset
INFO: write_value is 0x4
INFO: Channel 0: Set RX Reset
INFO: write_value is 0x6
INFO: check_reset_ack_n_status for current_dr_profile : 200G -----
INFO: Channel 0 : Checking tx reset ack 0 status...
INFO: tx_reset_ack_status_0 = 0xf
INFO: TX fully in reset state
INFO: Channel 0 : Checking tx reset ack 1 status...
INFO: tx_reset_ack_status_1 = 0xf
INFO: TX fully in reset state
INFO: Channel 0 : Checking rx reset ack status...
INFO: rx_reset_ack_status_0 = 0xf
INFO: RX fully in reset state
INFO: Channel 0 : Checking rx reset ack status...
INFO: rx_reset_ack_status_1 = 0xf
INFO: RX fully in reset state
INFO: Start DR selection-----
INFO: DR transition is 2x100G_4 -----
INFO: Channel: 0 Configuring ED to PMA_DIR 2x100G_4 ....
INFO: Wait for DR Ready....
INFO: configuring DR Profile 2x100G_4....
INFO: Trigger DR interrupt
INFO: Wait for DR interrupt Ack....
INFO: DR Request acknowledged
INFO: Wait for DR Config to be done....
INFO: DONE Reconfigure to 2x100G_4.
INFO: Set DR mode...
INFO: DR mode is 0x2
INFO: Channel 0: Release TX Reset
INFO: write_value is 0x2
INFO: Channel 0: Release RX Reset
INFO: write_value is 0x0
INFO: Channel 0 : Run test...
INFO: Read out probe data: 0x7f70
INFO: Data locked with no error
INFO: Test Pass!
*******
*******
INFO: Channel 0: Set TX Reset
INFO: write_value is 0x4
INFO: Channel 0: Set RX Reset
INFO: write_value is 0x6
INFO: check_reset_ack_n_status for current_dr_profile : 100G -----
INFO: Channel 0 : Checking tx reset ack 0 status...
INFO: tx_reset_ack_status_0 = 0xf
INFO: TX fully in reset state
INFO: Channel 0 : Checking tx reset ack 1 status...
INFO: tx_reset_ack_status_1 = 0xf
INFO: TX fully in reset state
INFO: Channel 0 : Checking rx reset ack status...
INFO: rx_reset_ack_status_0 = 0xf
INFO: RX fully in reset state
INFO: Channel 0 : Checking rx reset ack status...
INFO: rx_reset_ack_status_1 = 0xf
INFO: RX fully in reset state
INFO: Start DR selection-----
INFO: DR transition is 1x400G_8 -----
INFO: Channel: 0 Configuring ED to PMA_DIR 1x400G_8 ....
INFO: Wait for DR Ready....
INFO: configuring DR Profile 1x400G_8....
INFO: Trigger DR interrupt
INFO: Wait for DR interrupt Ack....
INFO: DR Request acknowledged
INFO: Wait for DR Config to be done....
INFO: DONE Reconfigure to 1x400G_8.
INFO: Set DR mode...
INFO: DR mode is 0x0
INFO: Channel 0: Release TX Reset
INFO: write_value is 0x2
INFO: Channel 0: Release RX Reset
INFO: write_value is 0x0
INFO: Channel 0 : Run test...
INFO: Read out probe data: 0x6b70
INFO: Data locked with no error
INFO: Test Pass!
*******
*******
Info: End of ftile_dphy_dr_test
Info: Test <ftile_dphy_dr_test> Passed
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