1.2. Generating the Design
- In the IP Catalog, locate and select F-Tile Dynamic Reconfiguration Suite Intel FPGA IP. The New IP Variation window appears.
- Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named as <your_ip>.ip.
- On the IP tab, specify the parameters for your IP core variation.
- On the Example Design tab, under Available Example Design, select the Protocol and Base Variant.
- On the Example Design tab, under Example Design Files, select the Simulation option to generate the testbench and the compilation-only project. Select the Synthesis option to generate the hardware design example. You must select at least one of the Simulation and Synthesis options to generate the design example.
- On the Example Design tab, under Generated HDL Format, select Verilog HDL.
- On the Example Design tab, under Target Development Kit, select the Board.
- If NONE is selected, the device OPN of the generated example design is your device selection while creating the Intel® Quartus® Prime project.
- If Intel® Agilex™ 7 I-Series Transceiver-SoC Development Kit is selected, the device OPN of the generated example design is AGIB027R31B1E2V (device OPN of the development kit). The VID settings is generated in the qsf file of the hardware design example.
- Click the Generate Example Design button. The Select Example Design Directory window appears.
If you want to modify the design example directory path or name from the default value (dr_f_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).
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