F-Tile Dynamic Reconfiguration Design Example User Guide

ID 710582
Date 4/03/2023
Public

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5.2. Ethernet to CPRI Design Example: Registers

Table 18.  Address Map for Ethernet to CPRI Variant
Address Range Mapping
0x1000_0000 – 0x1000_FFFF P0 Ethernet Registers
0x1080_0000 – 0x108F_FFFF P0 Transceiver Registers
0x1010_0000 – 0x1010_FFFF 25G Packet Client
0x0000_0000 – 0x0000_03FF Dynamic Reconfiguration Controller
0x2000_0000 – 0x2000_003F CPRI Soft Registers
0x2010_0000 – 0x2010_FFFF CPRI PCS Registers
0x2020_0000 – 0x202F_FFFF CPRI Transceiver Registers
Table 19.  Address Map for Ethernet to CPRI Variant (with 1GE)
Address Range Mapping
0x1000_0000 – 0x1000_FFFF P0 Ethernet Registers
0x1080_0000 – 0x108F_FFFF P0 Transceiver Registers
0x1010_0000 – 0x1010_FFFF 25G Packet Client
0x0000_0000 – 0x0000_03FF Dynamic Reconfiguration Controller
0x2000_0000 – 0x2000_003F CPRI Soft Registers
0x2010_0000 – 0x2010_FFFF CPRI PCS Registers
0x2020_0000 – 0x202F_FFFF CPRI Transceiver Registers
0x3000_0000 - 0x3000_03FF 1G Ethernet (Triple-Speed Ethernet) Registers
0x3001_0000 - 0x3001_0FFF 1G Ethernet (Direct-PHY) soft CSR Registers. For more information, refer to F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers.
0x3080_0000 - 0x308F_FFFF 1G Ethernet Transceiver Registers
0x3010_0000 - 0x3010_FFFF 1G Ethernet Traffic Controller