4.1.2. Ethernet Multirate Hardware Design Example
In the hardware design example, the reset, status, and control signals from packet clients, F-Tile Ethernet Multirate Intel® FPGA IP, and F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP in the example design are connected to In-System Sources and Probes IPs (ISSP). The hardware test scripts open service to the ISSP to read and drive the values. A JTAG host is instantiated to access the Avalon® memory-mapped interfaces.
The hardware design example executes the dynamic reconfiguration transition process, check the DUT IP status, clear the MAC statistics before sending 16 packets, and lastly display the MAC statistics.
|Base Variant (Startup IP/Mode)||Hardware Support||Target Variants||PTP mode|
|25G-1 with PTP||Yes||25G PTP
|100G-4||Yes||100G-4 with RS-FEC
2×50G-1 with RS-FEC
4×25G-1 with RS-FEC
|100G-4 with PTP||Yes||100G-4 with RS-FEC and PTP
100G-4 with PTP
100G-2 with RS-FEC and PTP
2×50G-1 with RS-FEC and PTP
4×25G-1 with RS-FEC and PTP
4×25G-1 with PTP
|400G-8||Yes||400G-8 with RS-FEC
2x200G-4 with RS-FEC
4x100G-2 with RS-FEC
|400G-8 with PTP||Yes||400G-8 with RS-FEC and PTP
2x200G-4 with RS-FEC and PTP
4x100G-2 RS-FEC with PTP
|FHT 400G-4||Yes||FHT 400G-4 with RS-FEC
FHT 1x200G-4 with RS-FEC
FHT 2x200G-2 with RS-FEC
FHT 2x100G-2 with RS-FEC
FHT 4x100G-1 RS-FEC
Hardware Flow for Design Example:
- For PTP enabled designs using Advance Accuracy Mode (i.e. 25GE-1 with RSFEC and PTP and 400G-8 with RSFEC and PTP), you must generate the routing delay information first before you run the main_script.tcl.
- For the steps required to generate this routing delay information, refer to Routing Delay Adjustment for Advanced Timestamp Accuracy Mode in F-tile Ethernet Intel FPGA Hard IP User Guide.
- Refer to steps 6b and 6c in the Hardware Design Example of F-tile Ethernet Intel FPGA Hard IP Design Example User Guide to add the external module and board trace value.
- For PTP enabled designs that target the Intel® Agilex™ 7 I-Series Transceiver-SoC Development Kit, the master TOD clock is sourced from U19, OUT1. You must program the OUT1 clock from the default of 166.6Mhz to the required 125Mhz frequency using the development kit's clock controller GUI. For designs which do not use PTP but target the Intel® Agilex™ 7 I-Series Transceiver-SoC Development kit, the default clock settings are sufficient and this step is not required.
- A successful run displays Test <ftile_eth_dr_test> Passed at System Console.
For more information to test the design example in hardware, refer to Testing the Hardware Design Example.
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