External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families
ID
710283
Date
3/06/2023
Public
2.1.1. Selecting Your External Memory Device
2.1.2. Selecting Your FPGA
2.1.3. Planning Your Pin Requirements
2.1.4. Planning Your FPGA Resources
2.1.5. Determining Your Board Layout
2.1.6. Specifying Parameters for Your External Memory Interface
2.1.7. Performing Functional Simulation
2.1.8. Adding Design Constraints
2.1.9. Compiling Your Design and Verifying Timing
2.1.10. Verifying and Debugging External Memory Interface Operation
3.1. DDR SDRAM Features
3.2. DDR2 SDRAM Features
3.3. DDR3 SDRAM Features
3.4. QDR, QDR II, and QDR II+ SRAM Features
3.5. RLDRAM II and RLDRAM 3 Features
3.6. LPDDR2 Features
3.7. Memory Selection
3.8. Example of High-Speed Memory in Embedded Processor
3.9. Example of High-Speed Memory in Telecom
3.10. Document Revision History
2. Recommended Design Flow
Intel® recommends that you create an example top-level file with the desired pin outs and all interface IP instantiated, which enables the Intel® Quartus® Prime software to validate your design and resource allocation before PCB and schematic sign off.
The following figure shows the design flow to provide the fastest out-of-the-box experience with external memory interfaces in Intel® FPGAs. This design flow assumes that you are using Intel® IP to implement the external memory interface.
Figure 3. External Memory Interfaces Design Flowchart
Refer to Getting Started with External Memory Interfaces for guidance in performing the recommended steps in creating a working and robust external memory interface.