External Memory Interface Handbook Volume 1: Intel® FPGA Memory Solution Introduction and Design Flow: For UniPHY-based Device Families
ID
710283
Date
3/06/2023
Public
2.1.1. Selecting Your External Memory Device
2.1.2. Selecting Your FPGA
2.1.3. Planning Your Pin Requirements
2.1.4. Planning Your FPGA Resources
2.1.5. Determining Your Board Layout
2.1.6. Specifying Parameters for Your External Memory Interface
2.1.7. Performing Functional Simulation
2.1.8. Adding Design Constraints
2.1.9. Compiling Your Design and Verifying Timing
2.1.10. Verifying and Debugging External Memory Interface Operation
3.1. DDR SDRAM Features
3.2. DDR2 SDRAM Features
3.3. DDR3 SDRAM Features
3.4. QDR, QDR II, and QDR II+ SRAM Features
3.5. RLDRAM II and RLDRAM 3 Features
3.6. LPDDR2 Features
3.7. Memory Selection
3.8. Example of High-Speed Memory in Embedded Processor
3.9. Example of High-Speed Memory in Telecom
3.10. Document Revision History
3.6. LPDDR2 Features
LPDDR2-S is a high-speed SDRAM device internally configured as a 4- or 8-bank memory. All LPDDR2 devices use double data rate architecture on the address and command bus to reduce the number of input pins in the system. The 10-bit address and command bus contains command, address, and bank/row buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edges of the clock.
LPDDR2-S2 and LPDDR2-S4 devices use double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially a 2n/4n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR2‑S2/S4 consists of a single 2n-bit wide /4n-bit wide, one clock cycle data transfer at the internal SDRAM core, and two/four corresponding n-bit wide, with one-half clock cycle data transfers at the I/O pins.