AN 941: Design Block Reuse Tutorial: for Intel® Agilex™ F-Series FPGA Development Board

ID 709312
Date 12/10/2021
Public
Document Table of Contents

1.4.5. Step 5: Hardware Verification (Optional)

You can now optionally verify the results of the Core Partition Reuse—Developer tutorial module in hardware by completing (Optional) Step 8: Device Programming.

After completing this tutorial module, LEDs D0-D1 map to the blinking_led core, and LEDs D3-D2 map to the top-level design.

Figure 10. Illumination of LEDs After Core Partition Reuse—Developer Tutorial Module