AN 941: Design Block Reuse Tutorial: for Intel® Agilex™ F-Series FPGA Development Board

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ID 709312
Date 12/10/2021
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Document Table of Contents
Document Table of Contents x
1. AN 941: Design Block Reuse Tutorial for Intel® Agilex™ F-Series FPGA Development Board
1. AN 941: Design Block Reuse Tutorial for Intel® Agilex™ F-Series FPGA Development Board x
1.1. Tutorial Overview 1.2. Tutorial Software and Hardware 1.3. Tutorial Files 1.4. Core Partition Reuse—Developer Tutorial 1.5. Core Partition Reuse—Consumer Tutorial 1.6. Root Partition Reuse—Developer Tutorial 1.7. Root Partition Reuse—Consumer Tutorial 1.8. (Optional) Step 8: Device Programming 1.9. Document Revision History for AN 941: Design Block Reuse Tutorial
1.4. Core Partition Reuse—Developer Tutorial x
Process Description Tutorial Steps Completed Tutorial Files Command-Line Alternative Step 1.4.1. Step 1: Define a Core Partition 1.4.2. Step 2: Compile and Export the Core Partition 1.4.3. Step 3: Create the Black Box File 1.4.4. Step 4: Copy Files to Consumer Project 1.4.5. Step 5: Hardware Verification (Optional)
1.5. Core Partition Reuse—Consumer Tutorial x
1.5.1. Step 1: Add Files and Run Synthesis 1.5.2. Step 2: Create a Partition for blinking_led 1.5.3. Step 3: Compile the Design 1.5.4. (Optional) Step 4: Hardware Verification
1.6. Root Partition Reuse—Developer Tutorial x
1.6.1. Step 1: Create a Reserved Core Partition 1.6.2. Step 2: Define a Logic Lock Region 1.6.3. Step 3: Compile and Export the Root Partition 1.6.4. Step 4: Copy Files to Consumer Project 1.6.5. Step 5: Hardware Verification (Optional)
1.7. Root Partition Reuse—Consumer Tutorial x
1.7.1. Step 1: Add the SDC and Root Partition 1.7.2. Step 2: Compile the Design 1.7.3. Step 3: Hardware Verification (Optional)
1. AN 941: Design Block Reuse Tutorial for Intel® Agilex™ F-Series FPGA Development Board

1.4. Core Partition Reuse—Developer Tutorial

Follow the steps in this tutorial module to develop a core partition for export and reuse in a Consumer project.

Process Description

In core partition reuse, the Developer defines, places, routes, and eventually exports a block of code within a design partition. The Developer then passes the exported .qdb to a Consumer.

Figure 3. Core Partition Reuse Flow

Reuse of the core partition also requires that the Developer provide a black box file to the Consumer. The Consumer must add the black box file to their project as a source file. The black box file defines the ports and port interface types for synthesis in the Consumer project. The Compiler ignores any other RTL that you include in the black box file.

You next assign the exported partition's .qdb file to a partition in the Consumer design. The .qdb file contains all of the information from the Developer project compilation snapshot. The Consumer can then reuse these preserved compilation results in the Consumer project. The exported synthesis snapshot includes only synthesis results. The exported final snapshot includes synthesis, placement, and routing results.

Tutorial Steps

This tutorial module includes the following steps:

Completed Tutorial Files

The Core_Partition_Reuse/Completed/Developer/ tutorial directory contains the completed files for this tutorial module.

Command-Line Alternative Step

You can skip Step 1: Define a Core Partition and Step 2: Compile and Export the Core Partition in this tutorial module by adding the following line to the Intel® Quartus® Prime Settings file (.qsf), and then running the Core_Partition_Reuse/Developer/Script/run.sh script. 

set_instance_assignment -name PARTITION blinking_led -to \
     u_blinking_led -entity top
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