AN 941: Design Block Reuse Tutorial: for Intel® Agilex™ F-Series FPGA Development Board

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ID 709312
Date 12/10/2021
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Document Table of Contents
Document Table of Contents x
1. AN 941: Design Block Reuse Tutorial for Intel® Agilex™ F-Series FPGA Development Board
1. AN 941: Design Block Reuse Tutorial for Intel® Agilex™ F-Series FPGA Development Board x
1.1. Tutorial Overview 1.2. Tutorial Software and Hardware 1.3. Tutorial Files 1.4. Core Partition Reuse—Developer Tutorial 1.5. Core Partition Reuse—Consumer Tutorial 1.6. Root Partition Reuse—Developer Tutorial 1.7. Root Partition Reuse—Consumer Tutorial 1.8. (Optional) Step 8: Device Programming 1.9. Document Revision History for AN 941: Design Block Reuse Tutorial
1.4. Core Partition Reuse—Developer Tutorial x
1.4.1. Step 1: Define a Core Partition 1.4.2. Step 2: Compile and Export the Core Partition 1.4.3. Step 3: Create the Black Box File 1.4.4. Step 4: Copy Files to Consumer Project 1.4.5. Step 5: Hardware Verification (Optional)
1.5. Core Partition Reuse—Consumer Tutorial x
1.5.1. Step 1: Add Files and Run Synthesis 1.5.2. Step 2: Create a Partition for blinking_led 1.5.3. Step 3: Compile the Design 1.5.4. (Optional) Step 4: Hardware Verification
1.6. Root Partition Reuse—Developer Tutorial x
1.6.1. Step 1: Create a Reserved Core Partition 1.6.2. Step 2: Define a Logic Lock Region 1.6.3. Step 3: Compile and Export the Root Partition 1.6.4. Step 4: Copy Files to Consumer Project 1.6.5. Step 5: Hardware Verification (Optional)
1.7. Root Partition Reuse—Consumer Tutorial x
1.7.1. Step 1: Add the SDC and Root Partition 1.7.2. Step 2: Compile the Design 1.7.3. Step 3: Hardware Verification (Optional)
1. AN 941: Design Block Reuse Tutorial for Intel® Agilex™ F-Series FPGA Development Board

1.4.2. Step 2: Compile and Export the Core Partition

Follow this step to run full compilation and manually export a final snapshot of your core partition. Alternatively, you can automate partition export each time you run compilation, as Step 1: Create a Reserved Core Partition describes later in this tutorial.
  1. To run full compilation of the design and create the final snapshot, double-click Compile Design on the Compilation Dashboard. The Timing Analyzer opens automatically when compilation is complete.
    Figure 7. Full Compilation Complete
  2. To export the core partition, click Project > Export Design Partition. Select blinking_led for the Partition name, and the final compilation Snapshot for export.
    Figure 8. Export Design Partition Dialog Box
    Note: Intel® FPGA IP targeting Intel® Agilex™ devices do not use entity-bound .sdc files by default. To use this option for Intel® Agilex™ devices, you must first bind the .sdc file to the entity in the .qsf. Refer to "Using Entity-bound SDC Files," in Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer.
  3. Confirm blinking_led.qdb as the Partition Database File name, and then click OK. The final blinking_led.qdb that you export preserves the complete placement and routing information from the original project when you reuse the block in a Consumer project.
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