AN 941: Design Block Reuse Tutorial: for Intel® Agilex™ F-Series FPGA Development Board

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ID 709312
Date 12/10/2021
Public
Document Table of Contents
Document Table of Contents x
1. AN 941: Design Block Reuse Tutorial for Intel® Agilex™ F-Series FPGA Development Board
1. AN 941: Design Block Reuse Tutorial for Intel® Agilex™ F-Series FPGA Development Board x
1.1. Tutorial Overview 1.2. Tutorial Software and Hardware 1.3. Tutorial Files 1.4. Core Partition Reuse—Developer Tutorial 1.5. Core Partition Reuse—Consumer Tutorial 1.6. Root Partition Reuse—Developer Tutorial 1.7. Root Partition Reuse—Consumer Tutorial 1.8. (Optional) Step 8: Device Programming 1.9. Document Revision History for AN 941: Design Block Reuse Tutorial
1.4. Core Partition Reuse—Developer Tutorial x
1.4.1. Step 1: Define a Core Partition 1.4.2. Step 2: Compile and Export the Core Partition 1.4.3. Step 3: Create the Black Box File 1.4.4. Step 4: Copy Files to Consumer Project 1.4.5. Step 5: Hardware Verification (Optional)
1.5. Core Partition Reuse—Consumer Tutorial x
1.5.1. Step 1: Add Files and Run Synthesis 1.5.2. Step 2: Create a Partition for blinking_led 1.5.3. Step 3: Compile the Design 1.5.4. (Optional) Step 4: Hardware Verification
1.6. Root Partition Reuse—Developer Tutorial x
1.6.1. Step 1: Create a Reserved Core Partition 1.6.2. Step 2: Define a Logic Lock Region 1.6.3. Step 3: Compile and Export the Root Partition 1.6.4. Step 4: Copy Files to Consumer Project 1.6.5. Step 5: Hardware Verification (Optional)
1.7. Root Partition Reuse—Consumer Tutorial x
1.7.1. Step 1: Add the SDC and Root Partition 1.7.2. Step 2: Compile the Design 1.7.3. Step 3: Hardware Verification (Optional)
1. AN 941: Design Block Reuse Tutorial for Intel® Agilex™ F-Series FPGA Development Board

1.5.4. (Optional) Step 4: Hardware Verification

You can now optionally verify the results of the Core Partition Reuse—Consumer Tutorial module in hardware by completing (Optional) Step 8: Device Programming.

After completing this tutorial module, LEDs D0-D1 map to the blinking_led core, and LEDs D3-D2 map to the top-level design.

Figure 14. Illumination of LEDs After Core Partition Reuse—Consumer Tutorial Module
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