AN 941: Design Block Reuse Tutorial: for Intel® Agilex™ F-Series FPGA Development Board

ID 709312
Date 12/10/2021
Public
Document Table of Contents

1.7.3. Step 3: Hardware Verification (Optional)

You can now verify the results of the Root Partition Reuse—Consumer Tutorial module in hardware by completing the steps in (Optional) Step 8: Device Programming.

After completing this tutorial module, LEDs D0-D1 map to the blinking_led core, and LEDs D3-D2 map to the top-level design.

Figure 25. Illumination of LEDs after the Root Partition Reuse—Consumer Tutorial