eCPRI Intel® FPGA IP Design Example User Guide

ID 683837
Date 7/01/2022
Public

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2.2. Hardware Design Example

Figure 4. Block Diagram for Intel® Agilex™ F-tile Designs
Figure 5. Block Diagram for Intel® Agilex™ E-tile Designs
Figure 6. Block Diagram for Intel® Stratix® 10 Designs
Figure 7. Block Diagram for Intel® Arria® 10 Designs

The eCPRI Intel® FPGA IP core hardware design example includes the following components:

eCPRI Intel® FPGA IP

Accepts data from the traffic generators instantiated within the test wrapper and prioritize the data for transmission to the Ethernet IP.

Ethernet IP

  • F-tile Ethernet Intel FPGA Hard IP ( Intel® Agilex™ F-tile designs)
  • E-tile Hard IP for Ethernet ( Intel® Stratix® 10 or Intel® Agilex™ E-tile designs)
  • 25G Ethernet Intel® Stratix® 10 IP ( Intel® Stratix® 10 H-tile designs)
  • Low Latency Ethernet 10G MAC IP and 1G/10GbE and 10GBASE-KR PHY IP ( Intel® Arria® 10 designs)

Precision Time Protocol (PTP) IO PLL

For Intel® Stratix® 10 H-tile designs—Instantiated to generate the latency measurement input reference clock for the Ethernet IP and sampling clock for Time of Day (TOD) subsystem. For 25G Ethernet Intel Stratix 10 FPGA IP with the IEEE 1588v2 feature, Intel® recommends you to set the frequency of this clock to 156.25 MHz. Refer to the 25G Ethernet Intel Stratix 10 FPGA IP User Guide and Intel Stratix 10 H-tile Transceiver PHY User Guide for more information. The PTP IOPLL also generates the reference clock for the eCPRI IO PLL in the cascading manner.

For Intel® Arria® 10 designs—Instantiated to generate the 312.5 MHz and 156.25 MHz clock inputs for the Low Latency Ethernet 10G MAC IP and 1G/10GbE, 10GBASE-KR PHY IP, and eCPRI IP .

eCPRI IO PLL

Generates core clock output of 390.625 MHz for the TX and RX path of the eCPRI IP, and traffic components.

Note: This block is only present in the design example generated for Intel® Stratix® 10 and Intel® Agilex™ devices.

IWF Type 0

Converts CPRI MAC data packet into eCPRI packet. This block sits between the CPRI MAC and eCPRI IP as shown in block diagram above. The conversion works only for message type 0,2, 6, and 7.
Note: The current version of the eCPRI Intel FPGA IP only supports IWF type 0. For Intel® Agilex™ F-tile devices, the design example enabled with IWF feature is not supported.
When you generate the design example with Interworking Function (IWF) Support parameter turned off, the packet traffic flows directly from the test wrapper module to the Avalon-ST source/sink interface and external source/sink interface of the eCPRI IP.

When you generate the design example with Interworking Function (IWF) Support parameter turned on, the packet traffic flows to the IWF Avalon-ST sink interface from the test wrapper module first, and coming out from IWF Avalon-ST source interface to the eCPRI Avalon-ST source/sink interface.

CPRI MAC

Provides the CPRI part of the layer 1 and full layer 2 protocols for the transfer of user plane, C&M, and synchronization information between REC and RE as well as between two RE,

CPRI PHY

Provides the remaining part of CPRI layer 1 protocol for line coding, bit error correction/detection, and etc.
Note: The CPRI MAC and CPRI PHY IP instantiated in this design example are configured to be running at single CPRI line rate 9.8 Gbps only. The design example does not support line rate auto-negotiation in the current release.

Test Wrapper

Consists of traffic generators and checkers which generates different set of data packets to the Avalon Streaming (Avalon-ST) interfaces of the eCPRI IP as below:
  • eCPRI packets to the Avalon-ST source/sink interfaces (IWF feature disabled):
    • Only supports message type 2.
    • Back-to-back mode generation with incremental pattern mode generation and payload size of 72 bytes for each packet.
    • Configurable via CSR to run in either non-continuous or continuous mode.
    • TX/RX packet statistic status available to access via CSR.
  • eCPRI packets to the Avalon-ST source/sink interfaces (IWF feature enabled):
    • Only supports message type 0 in current release.
    • Incremental pattern mode generation with interpacket gap generation and payload size of 240 bytes for each packet.
    • Configurable via CSR to run in either non-continuous or continuous mode.
    • TX/RX packet statistic status available to access via CSR.
  • Precision Time Protocol (1588 PTP) packet and non-PTP miscellaneous packets to the External source/sink interfaces:
    • Static Ethernet header generation with pre-defined parameters: Ethertype- 0x88F7, Message type- Opcode 0 (Sync), and PTP version-0.
    • Pre-defined pattern mode generation with interpacket gap of 2 cycles and payload size of 57 bytes for each packet.
    • 128 packets are generated in the period of every one second.
    • Configurable via CSR to run in either non-continuous or continuous mode.
    • TX/RX packet statistic status available to access via CSR.
  • External non-PTP miscellaneous packets:
    • Static Ethernet Header generation with pre-defined parameter, Ethertype- 0x8100 (non-PTP).
    • PRBS pattern mode generation with interpacket gap of 2 cycles and payload size of 128 bytes for each packet.
    • Configurable via CSR to run in either non-continuous or continuous mode.
    • TX/RX packet statistic status available to access via CSR.

Time of Day (TOD) subsystem

Contains two IEEE 1588 TOD modules for both TX and RX, and one IEEE 1588 TOD Synchronizer module generated by Intel® Quartus® Prime software.

Nios® II Subsystem

Consists of Avalon-MM bridge that allows Avalon-MM data arbitration between Nios® II processor, test wrapper, and Avalon® -MM address decoder blocks.

Nios® II is responsible to perform data rate switching based on the output from test wrapper's rate_switch register value. This block programs the necessary register once it receives command from the test wrapper.

Note: This block is not present in the design example generated for Intel® Arria® 10 and Intel® Agilex™ F-tile devices.

System Console

Provides a user-friendly interface for you to do first-level debugging and monitor status of the IP, and the traffic generators and checkers.

Demo Control

This module consists of reset synchronizer modules, and In-system Source and Probe (ISSP) modules for design system debugging and initialization process.

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