eCPRI Intel® FPGA IP Design Example User Guide

ID 683837
Date 7/01/2022
Public

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1.3. Directory Structure

The eCPRI IP core design example file directories contain the following generated files for the design example.
Figure 3. Directory Structure of the Generated Example Design
Table 1.   eCPRI Intel® FPGA IP Core Testbench File Descriptions

File Names

Description

Key Testbench and Simulation Files

<design_example_dir>/simulation/testbench/ecpri_tb.sv Top-level testbench file. The testbench instantiates the DUT wrapper and runs Verilog HDL tasks to generate and accept packets.
<design_example_dir>/simulation/testbench/ecpri_ed.sv DUT wrapper that instantiates DUT and other testbench components.
<design_example_dir>/simulation/ed_fw/flow.c C-code source file.

Testbench Scripts

<design_example_dir>/simulation/setup_scripts/mentor/run_vsim.do The Siemens* EDA QuestaSim* script to run the testbench.
<design_example_dir>/simulation/setup_scripts/synopsys/vcs/run_vcs.sh The Synopsys* VCS* script to run the testbench.
<design_example_dir>/simulation/setup_scripts/synopsys/vcsmx/run_vcsmx.sh The Synopsys* VCS* MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench.
<design_example_dir>/simulation/setup_scripts/aldec/run_rivierapro.tcl The Aldec* Riviera-PRO* script to run the testbench.
<design_example_dir>/simulation/setup_scripts/xcelium/run_xcelium.sh The Cadence* Xcelium* script to run the testbench.
Table 2.   eCPRI Intel® FPGA IP Core Hardware Design Example File Descriptions
File Names Descriptions
<design_example_dir>/synthesis/quartus/ecpri_ed.qpf Intel® Quartus® Prime project file.
<design_example_dir>/synthesis/quartus/ecpri_ed.qsf Intel® Quartus® Prime project setting file.
<design_example_dir>/synthesis/quartus/ecpri_ed.sdc Synopsys Design Constraints files. You can copy and modify these files for your own Intel® Stratix® 10 design.
<design_example_dir>/synthesis/testbench/ecpri_ed_top.sv Top-level Verilog HDL design example file.
<design_example_dir>/synthesis/testbench/ecpri_ed.sv DUT wrapper that instantiates DUT and other testbench components.
<design_example_dir>/synthesis/quartus/ecpri_s10.tcl Main file for accessing System Console (Available in Intel® Stratix® 10 H-tile and E-tile designs).
<design_example_dir>/synthesis/quartus/ecpri_a10.tcl Main file for accessing System Console (Available in Intel® Arria® 10 designs).
<design_example_dir>/synthesis/quartus/ecpri_agilex.tcl Main file for accessing System Console (Available in Intel® Agilex™ designs).

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