eCPRI Intel® FPGA IP Design Example User Guide

ID 683837
Date 7/01/2022
Public

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1.7. Testing the eCPRI Intel FPGA IP Design Example

After you compile the eCPRI Intel® FPGA IP core design example and configure it on your Intel® FPGA device, you can use the System Console to program the IP core and its embedded Native PHY IP core registers.

To turn on the System Console and test the hardware design example, follow these steps:

  1. After the hardware design example is configured on the Intel® device, in the Intel® Quartus® Prime Pro Edition software, on the Tools menu, click System Debugging Tools > System Console.
  2. In the Tcl Console pane, change directory to <design_example_dir>/synthesis/quartus/hardware_test and type the following command to open a connection to the JTAG master and start the test:
    • source ecpri_agilex.tcl for Intel® Agilex™ designs
    • source ecpri_s10.tcl for Intel® Stratix® 10 designs
    • source ecpri_a10.tcl for Intel® Arria® 10 designs
  3. For your Intel® Stratix® 10 or Intel® Agilex™ E-tile device variations, you must perform either an internal or external loopback command once after you program the .sof file:
    1. Modify TEST_MODE variable in the flow.c file to select the loopback mode:
      TEST_MODE Action
      0 Serial loopback enable for simulation only
      1 Serial loopback enable for hardware only
      2 Serial loopback and calibration
      3 Calibration only
      You must recompile and regenerate the NIOS II software whenever you change the flow.c file.
    2. Regenerate the .elf file and program to the board one more time and reprogram the .sof file.
  4. Test the design operation through the commands supported in the system console script. The system console script provides useful commands for reading statistics and features enabling in the design.
    Table 4.  System Console Script Commands
    Command Description
    loop_on Enables TX to RX internal serial loopback. Use for Intel® Stratix® 10 H-tile and Intel® Arria® 10 devices only.
    loop_off Disables TX to RX internal serial loopback. Use for Intel® Stratix® 10 H-tile and Intel® Arria® 10 devices only.
    link_init_int_lpbk Enables TX to RX internal serial loopback within the transceiver and performs the transceiver calibration flow. Applicable to the Intel® Stratix® 10 E-tile and Intel® Agilex™ E-tile designs only.
    link_init_ext_lpbk Enables TX to RX external loopback and performs the transceiver calibration flow. Applicable to the Intel® Stratix® 10 E-tile and Intel® Agilex™ E-tile designs only.
    traffic_gen_disable Disables the traffic generator and checker.
    chkmac_stats Displays the statistics for the Ethernet MAC.
    read_test_statistics Display the error statistics for traffic generator and checkers.
    ext_continuous_mode_en Resets the entire design system, and enables the traffic generator to generate continuous traffic packets.
    dr_25g_to_10g_etile Switches the data rate of the Ethernet MAC from 25G to 10G. Use for the Intel® Stratix® 10 E-tile and Intel® Agilex™ E-tile devices only.
    dr_25g_to_10g_htile Switches the data rate of the Ethernet MAC from 25G to 10G. Use for H-tile devices only
    dr_10g_to_25g_etile Switches the data rate of the Ethernet MAC from 10G to 25G. Use for the Intel® Stratix® 10 E-tile and Intel® Agilex™ E-tile devices only.
    dr_25g_to_10g_htile Switches the data rate of the Ethernet MAC from 10G to 25G. Use for H-tile devices only.
    The following sample output illustrates a successful test run:
    System Console Printout (Number of Channels = 1)
    
    Channel 0 EXT PTP TX SOP Count: 256
    Channel 0 EXT PTP TX EOP Count: 256
    Channel 0 EXT MISC TX SOP Count: 36328972
    Channel 0 EXT MISC TX EOP Count: 36369511
    Channel 0 EXT RX SOP Count: 36410364
    Channel 0 EXT RX EOP Count: 36449971
    Channel 0 EXT Checker Errors: 0
    Channel 0 EXT Checker Error Counts: 0
    Channel 0 EXT PTP Fingerprint Errors: 0
    Channel 0 EXT PTP Fingerprint Error Counts: 0
    Channel 0 TX SOP Count: 1337760
    Channel 0 TX EOP Count: 1339229
    Channel 0 RX SOP Count: 1340728
    Channel 0 RX EOP Count: 1342555
    Channel 0 Checker Errors: 0
    Channel 0 Checker Error Counts: 0
     ==========================================================================================
                ETHERNET MAC STATISTICS FOR Channel 0 (Rx)     
     ==========================================================================================
    Fragmented Frames                 		: 0 
    Jabbered Frames                   		: 0 
    Right Size with FCS Err Frames     		: 0 
    Multicast data  Err Frames        		: 0 
    Broadcast data Err  Frames        		: 0 
    Unicast data Err  Frames         			: 0 
    64 Byte Frames                    		: 3641342 
    65 - 127 Byte Frames              		: 0 
    128 - 255 Byte Frames             		: 37404809 
    256 - 511 Byte Frames             		: 29128650 
    512 - 1023 Byte Frames            		: 0 
    1024 - 1518 Byte Frames           		: 0 
    1519 - MAX Byte Frames            		: 0 
    > MAX Byte Frames                 		: 0 
    Multicast data  OK  Frame       	  		: 70174801 
    Broadcast data OK   Frame        	 		: 0 
    Unicast data OK   Frames          		: 0 
    Multicast Control Frames          		: 0 
    Broadcast Control Frames          		: 0 
    Unicast Control Frames            		: 0 
    Pause Control Frames              		: 0 
    Payload Octets OK                 		: 11505935812 
    Frame Octets OK                    		: 12918701444 
    Rx Maximum Frame Length				: 1518 
    Any Size with FCS Err Frame			: 0 
    Multicast control  Err Frame     			: 0 
    Broadcast control Err  Frame     			: 0 
    Unicast control Err  Frames      			: 0 
    Pause control Err  Frames				: 0 
    Rx Frame Starts                  			: 70174801 
    
    The following is the sample output for the 25G to 10G DR test run:
    System Console Printout (25G to 10G DR E-tile)
    
    Initiate Dynamic Reconfiguration for Ethernet 25G -> 10G
    DR Successful 25G -> 10G
    RX PHY Register Access: Checking Clock Frequencies (KHz)
    TXCLK :16114  (KHZ)
    RXCLK :16113  (KHZ)
     RX PHY Status Polling 
     Rx Frequency Lock Status		0x0000000f 
     Mac Clock in OK Condition? 	0x00000001 
     Rx Frame Error ?				0x00000000 
     Rx PHY Fully Aligned? 		0x00000001 
    Polling RX PHY Channel 0
    RX PHY Channel 0 is up and running! 
    
    System Console Printout (25G to 10G DR H-tile)
    
    Initiate Dynamic Reconfiguration for Ethernet 25G -> 10G
    DR Successful 25G -> 10G
    RX PHY Register Access: Checking Clock Frequencies (KHz)
    TXCLK :15625  (KHZ)
    RXCLK :15625  (KHZ)
     RX PHY Status Polling 
     Rx Frequency Lock Status		0x00000001 
     Mac Clock in OK Condition? 	0x00000007 
     Rx Frame Error ?				0x00000000 
     Rx PHY Fully Aligned? 		0x00000001 
    Polling RX PHY Channel 0
    RX PHY Channel 0 is up and running! 
    
    System Console Printout (10G to 25G DR E-tile)
    
    Initiate Dynamic Reconfiguration for Ethernet 10G -> 25G
    DR Successful 10G -> 25G
    RX PHY Register Access: Checking Clock Frequencies (KHz)
    TXCLK :40283  (KHZ)
    RXCLK :40283  (KHZ)
     RX PHY Status Polling 
     Rx Frequency Lock Status		0x0000000f 
     Mac Clock in OK Condition? 	0x00000001 
     Rx Frame Error ?				0x00000000 
     Rx PHY Fully Aligned? 		0x00000001 
    Polling RX PHY Channel 0
    RX PHY Channel 0 is up and running! 
    
    System Console Printout (10G to 25G DR H-tile)
    
    Initiate Dynamic Reconfiguration for Ethernet 10G -> 25G
    DR Successful 10G -> 25G
    RX PHY Register Access: Checking Clock Frequencies (KHz)
    TXCLK :39061  (KHZ)
    RXCLK :39063  (KHZ)
     RX PHY Status Polling 
     Rx Frequency Lock Status		0x00000001 
     Mac Clock in OK Condition? 	0x00000007 
     Rx Frame Error ?				0x00000000 
     Rx PHY Fully Aligned? 		0x00000001 
    Polling RX PHY Channel 0
    RX PHY Channel 0 is up and running! 
    

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