eCPRI Intel® FPGA IP Design Example User Guide

ID 683837
Date 7/01/2022
Public

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2.4. Interface Signals

Table 5.  Design Example Interface Signals
Signal Direction Description
clk_ref Input Reference clock for the Ethernet MAC.
  • For Intel® Stratix® 10 E-tile, Intel® Agilex™ E-tile and F-tile designs, 156.25 MHz clock input for the E-tile Ethernet Hard IP core or F-tile Ethernet Hard IP core. Connect to i_clk_ref[0] in the Ethernet Hard IP.
  • For Intel® Stratix® 10 H-tile designs, a 322.2625 MHz clock input for the Transceiver ATX PLL and 25G Ethernet IP. Connect to pll_refclk0[0] in the Transceiver ATX PLL and clk_ref[0] in 25G Ethernet IP.
  • For Intel® Arria® 10 designs, a 322.265625 MHz clock input for the Transceiver ATX PLL and 1G/10GbE and 10GBase-KR PHY IP. Connect to pll_refclk0[0] in the Transceiver ATX PLL and rx_cdr_ref_clk_10g[0] in the 1G/10GbE and 10G BASE-KR PHY IP.
tod_sync_sampling_clk Input For Intel Arria 10 designs, a 250 MHz clock input for TOD subsystem.
clk100 Input Management clock. This clock is used to generate latency_clk for PTP.

Drive at 100 MHz.

mgmt_reset_n Input Reset signal for Nios® II system.
tx_serial Output TX serial data. Supports up to 4 channels.
rx_serial Input RX serial data. Supports up to 4 channels.
iwf_cpri_ehip_ref_clk Input E-tile CPRI PHY reference clock input. This clock is only present in Intel® Stratix® 10 E-tile and Intel® Agilex™ E-tile designs.

Drive at 153.6 MHz for 9.8 Gbps CPRI line rate.

iwf_cpri_pll_refclk0 Output CPRI TX PLL reference clock.
  • For Intel® Stratix® 10 H-tile designs: Drive at 307.2 MHz for CPRI data rate 9.8 Gbps.
  • For Intel® Stratix® 10 E-tile and Intel® Agilex™ E-tile designs: Drive at 156.25 MHz for CPRI data rate 9.8 Gbps.
iwf_cpri_xcvr_cdr_refclk Output CPRI receiver CDR reference clock. This clock is only present in Intel® Stratix® 10 H-tile designs.

Drive at 307.2 MHz for 9.8 Gbps CPRI line rate.

iwf_cpri_xcvr_txdataout Output CPRI transmit serial data. Supports up to 4 channels.
iwf_cpri_xcvr_rxdatain Output CPRI receiver serial data. Supports up to 4 channels.
cpri_gmii_clk Input CPRI GMII 125 MHz input clock.

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