25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide
Version Information
Updated for: |
---|
Intel® Quartus® Prime Design Suite 19.2 |
IP Version 19.2.0 |
1. 25G Ethernet Intel FPGA IP Quick Start Guide
The 25G Ethernet (25GbE) Intel® FPGA IP core for Intel® Stratix® 10 devices provides the capability of generating design examples for selected configurations.
1.1. Directory Structure
- The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.
- The compilation-only design example is located in <design_example_dir>/compilation_test_design.
- The hardware configuration and test files (the design example in hardware) are located in <design_example_dir>/hardware_test_design.
File Names |
Description |
---|---|
eth_ex_25g.qpf | Intel® Quartus® Prime project file. |
eth_ex_25g.qsf | Intel® Quartus® Prime project settings file. |
eth_ex_25g.sdc | Synopsys Design Constraints file. You can copy and modify this file for your own 25GbE Intel® FPGA IP core design. |
eth_ex_25g.v | Top-level Verilog HDL design example file. Single-channel design uses Verilog file. |
common/ | Hardware design example support files. |
hwtest/main.tcl | Main file for accessing System Console. |
1.2. Generating the Design Example
Follow these steps to generate the hardware design example and testbench:
- In the Intel® Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device.
- In the IP Catalog, locate and select 25G Ethernet Intel® FPGA IP . The New IP Variation window appears.
- Specify a top-level name for your IP variation and click OK. The parameter editor adds the top-level .ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
- In the
Intel®
Quartus® Prime Pro Edition software, you must select a specific
Intel®
Stratix® 10 device in the Device field, or keep the default device that the
Intel®
Quartus® Prime software proposes. Note: The hardware design example overwrites the selection with the device on the target board. You specify the target board from the menu of design example options in the Example Design tab (Step 8).
- Click OK. The parameter editor appears.
- On the IP tab, specify the parameters for your IP core variation.
- On the Example Design tab, for
Example Design Files, select the Simulation option to generate the testbench, and select the
Synthesis option to generate the hardware design
example. Only Verilog HDL files are generated.Note: A functional VHDL IP core is not available. Specify Verilog HDL only, for your IP core design example.
- For Target Development Kit, select the
Stratix®
10 GX Signal Integrity L-Tile (Prod) Development Kit.Note: The target device of the generated hardware example design is for Intel® Stratix® 10 GX Signal Integrity L-Tile (Production) Development Kit (1SX280LU2F50E1VG) and may differ from your selected device. The target device can be changed after hardware design example generation has completed. For the procedure to change the target device, refer to Changing Target Device in Hardware Design Example.
- Click Generate Example Design. The Select Example Design Directory window appears.
- If you want to modify the design example directory path or name from the defaults displayed (alt_e25s10_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).
- Click OK.
1.2.1. Design Example Parameters
Parameter | Description |
---|---|
Example Design | Available example designs for the IP parameter settings. |
Example Design Files |
The files to generate for the different development phase.
|
Generate File Format | The format of the RTL files for simulation—Verilog. |
Select Board | Supported hardware for design implementation. When you select
an Intel FPGA development board,
use device
1SX280LU2F50E1VG as the Target
Device
for design example generation.
If this menu is not available, there is no supported board for the options that you select. Stratix® 10 GX Signal Integrity L-Tile (Prod) Development Kit: This option allows you to test the design example on the selected Intel FPGA IP development kit. This option automatically selects the Target Device of 1SX280LU2F50E1VG. If your board revision has a different device grade, you can change the target device. None: This option excludes the hardware aspects for the design example. |
1.3. Simulating the 25G Ethernet Intel FPGA IP Design Example Testbench
1.3.1. Procedure
- At the command prompt, change the working directory to <design_example_dir>/example_testbench.
-
Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator.
Table 3. Steps to Simulate the Testbench Simulator Instructions ModelSim* In the command line, type vsim -do run_vsim.do. If you prefer to simulate without bringing up the ModelSim* GUI, type vsim -c -do run_vsim.do.
Note: The ModelSim* -AE and ModelSim* -ASE simulators cannot simulate this IP core. You must use another supported ModelSim* simulator such as ModelSim* SE.VCS* In the command line, type sh run_vcs.sh NCSim In the command line, type sh run_ncsim.sh Xcelium* In the command line, type sh run_xcelium.sh
Simulation Passed.or
Testbench complete.After successful completion, you can analyze the results.
1.4. Compiling and Configuring the Design Example in Hardware
1.4.1. Procedure
- Launch the Intel® Quartus® Prime Pro Edition software and select Processing > Start Compilation to compile the design.
-
After you generate an SRAM object file .sof, follow these steps to program the hardware design example on the
Intel®
Stratix® 10 device:
- On the Tools menu, click Programmer.
- In the Programmer, click Hardware Setup.
- Select a programming device.
- Select and add the Intel® Stratix® 10 GX board to your Intel® Quartus® Prime Pro Edition session.
- Ensure that Mode is set to JTAG.
- Select the Intel® Stratix® 10 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
- In the row with your .sof, check the box for the .sof.
- Check the box in the Program/Configure column.
- Click Start.
Note: This design targets the Intel® Stratix® 10 device. Please contact your Intel® FPGA representative to inquire about a platform suitable to run this hardware example.
1.5. Changing Target Device in Hardware Design Example
If you have selected Intel® Stratix® 10 GX Signal Integrity L-Tile (Production) Development Kit as your target device, the 25G Ethernet Intel® FPGA IP core generates a hardware example design for target device 1SX280LU2F50E1VG. This device may differ from the device on your development kit.
1.5.1. Procedure
To change the target device in your hardware design example, follow these steps:
- Launch the Intel® Quartus® Prime Pro Edition software and open the hardware test project file /hardware_test_design/eth_ex_25g.qpf.
- On the Assignments menu, click Device. The Device dialog box appears.
- In the Device dialog box, select 1SG280LU2F50E2VG (L-tile) or 1SG280HU1F50E2VG (H-tile) in the target device table that matches the device part number on your development kit. Refer to the Stratix® 10 GX Signal Integrity Development Kit link on the Intel® website for more information.
-
A prompt appears when you select a device, as shown in the figure below. Select No to preserve the generated pin assignments and I/O assignments.
Figure 5. Intel® Quartus® Prime Prompt for Device Selection
-
If you select 1SG280HU2F50E2VG (H-Tile GX) as your target device, click Upgrade IP Components in the Project menu, select 25G Ethernet FPGA IP from the list of IP components, and click Upgrade in Editor. Regenerate this IP component.
Note: If you select 1SG280LU1F50E2VG (L-Tile GX) as your target device, skip this step if you are using the same Quartus and IP version.
- Modify the pin assignment of cpu_resetn port to pin AW10 through Pin Planner or Assignment Editor in the Intel® Quartus® Prime Pro Edition. No other pin assignment modifications are required for the design example. When you generate the design example targeting other Intel® Stratix® 10 development kits, refer to the respective development kit user guides for pin assignment.
- Perform full compilation of your design.
1.6. Testing the 25G Ethernet Intel FPGA IP Design in Hardware
1.6.1. Procedure
To turn on the System Console and test the hardware design example, follow these steps:
- In the Intel® Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
- In the Tcl Console pane, type cd hwtest to change directory to /hardware_test_design/hwtest.
- Type source main.tcl to open a connection to the JTAG master.
2. 10G/25G Ethernet Single-Channel Design Example for Intel Stratix 10 Devices
Generate the design example from the Example Design tab of the 25G Ethernet Intel® FPGA IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature. You can also choose to generate the design with or without the Reed-Solomon Forward Error Correction (RS-FEC) feature.
2.1. Features
- Supports single Ethernet channel operating at either 10G or 25G.
- Generate design example with IEEE 1588v2 feature.
- Generate design example with RS-FEC feature.
- Generates design example separately from Intel® Stratix® 10 Transceiver Native PHY.
- Provides testbench and simulation script.
2.2. Hardware and Software Requirements
- Intel® Quartus® Prime Pro Edition software.
- ModelSim* -SE, NCSim (Verilog only), VCS* , and Xcelium* simulator.
- Intel® Stratix® 10 GX Signal Integrity L-Tile (Production) Development Kit (1SX280LU2F50E1VG) for hardware testing.
2.3. Functional Description
The 10G/25G Ethernet single-channel design example consists of two core variants—MAC+PCS+PMA and MAC+PCS. The following block diagrams show the design components and the top-level signals of the two core variants in the 10G/25G Ethernet single-channel design example.
2.3.1. Design Components
Component | Description |
---|---|
25G Ethernet Intel® FPGA IP |
Consists of MAC, PCS, and Transceiver PHY, with the following configuration:
For the design example with the IEEE 1588 feature, the following additional parameters are configured:
For the design example with the RS-FEC feature, the following additional parameter is configured:
|
Reconfiguration Sequencer | Reconfigures the transceiver channel speed from 10 Gbps to 25 Gbps, and vice versa. |
ATX PLL | Generates TX serial clocks for the 10G and 25G transceivers. |
Client logic | Consists of:
|
Source and Probe | Source and probe signals, including system reset input signal, which you can use for debugging. |
Design Components for the IEEE 1588v2 Feature | |
Sampling PLL | Generates the clocks for the IEEE 1588v2 design components.
|
Time-of-day (ToD) Sync | Synchronizes the 10G and 25G ToDs. |
ToD Tx | ToD for transmit paths for the 10G and 25G transceivers. |
ToD Rx | ToD for receive paths for the 10G and 25G transceivers. |
Master Precision Time Protocol (PTP) | Master PTP consists of a packet generator and a packet receiver.
|
Slave PTP | Slave PTP consists of a packet generator, a packet receiver, and packet compute.
|
2.4. Simulation
2.4.1. Testbench
Component | Description |
---|---|
Device under test (DUT) | The 25G Ethernet Intel® FPGA IP core. |
Reconfiguration Sequencer | Reconfigures the transceiver channel speed from 10 Gbps to 25 Gbps, and vice versa. |
Ethernet Packet Generator and Packet Monitor |
|
ATX PLL | Generates a TX serial clock for the Intel® Stratix® 10 10G/25G transceiver which is wrapped in the 25G Ethernet Intel® FPGA IP core. |
2.4.2. Simulation Design Example Components
File Name | Description |
---|---|
Testbench and Simulation Files | |
basic_avl_tb_top.sv | Top-level testbench file. The testbench instantiates the DUT, performs Avalon® memory-mapped configuration on design components and client logic, and sends and receives packet to or from the 25G Ethernet Intel® FPGA IP. |
Testbench Scripts | |
run_vsim.do | The ModelSim script to run the testbench. |
run_vcs.sh | The Synopsys VCS* script to run the testbench. |
run_ncsim.sh | The Cadence NCSim script to run the testbench. |
run_xcelium.sh | The Xcelium* script to run the testbench. |
2.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature
The simulation test case performs the following actions:
- Instantiates 25G Ethernet Intel® FPGA IP and ATX PLL.
- Starts up the design example with an operating speed of 25G.
- Waits for RX clock and PHY status signal to settle.
- Prints PHY status.
- Sends and receives 10 valid data on 25G speed.
- Performs channel reset and switches to 10G speed.
- Waits for RX clock and PHY status signal to settle.
- Prints PHY status.
- Sends and receives another 10 valid data on 10G speed.
- Performs channel reset and switches to 25G speed.
- Waits for RX clock and PHY status signal to settle.
- Prints PHY status.
- Sends and receives another 10 valid data on 25G speed.
- Analyzes the results. The successful testbench displays "Simulation PASSED.".
The following sample output illustrates a successful simulation test run:
Waiting for RX alignment RX deskew locked RX lane alignmnet locked TX enabled ** Sending Packet 1... ** Sending Packet 2... ** Sending Packet 3... ** Sending Packet 4... ** Sending Packet 5... ** Sending Packet 6... ** Sending Packet 7... ** Sending Packet 8... ** Received Packet 1... ** Received Packet 2... ** Sending Packet 9... ** Sending Packet 10... ** Received Packet 3... ** Received Packet 4... ** Received Packet 5... ** Received Packet 7... ** Received Packet 8... ** Received Packet 9... ** Received Packet 10... Switching to 10G mode: 10G Reconfig start Switching to 10G mode: 10G Reconfig End Waiting for RX alignment RX deskew locked RX lane alignment locked TX enabled ** Sending Packet 1... ** Sending Packet 2... ** Sending Packet 3... ** Sending Packet 4... ** Sending Packet 5... ** Sending Packet 6... ** Sending Packet 7... ** Sending Packet 8... ** Received Packet 1... ** Received Packet 2... ** Sending Packet 9... ** Sending Packet 10... ** Received Packet 3... ** Received Packet 4... ** Received Packet 5... ** Received Packet 7... ** Received Packet 8... ** Received Packet 9... ** Received Packet 10... Switching to 25G mode: 25G Reconfig start Switching to 25G mode: 25G Reconfig End Waiting for RX alignment RX deskew locked RX lane alignment locked TX enabled ** Sending Packet 1... ** Sending Packet 2... ** Sending Packet 3... ** Sending Packet 4... ** Sending Packet 5... ** Sending Packet 6... ** Sending Packet 7... ** Sending Packet 8... ** Received Packet 1... ** Received Packet 2... ** Sending Packet 9... ** Sending Packet 10... ** Received Packet 3... ** Received Packet 4... ** Received Packet 5... ** Received Packet 7... ** Received Packet 8... ** Received Packet 9... ** Received Packet 10... ** ** Testbench complete. **
2.4.4. Test Case—Design Example with the IEEE 1588v2 Feature
The simulation test case performs the following actions:
- Instantiates 25G Ethernet Intel® FPGA IP, ATX PLL, and IO PLL (sampling PLL).
- Starts up the design example with an operating speed of 25G.
- Waits for RX clock and PHY status signal to settle.
- Prints PHY status.
- Checks for 10 valid data on 25G speed.
- Switches to 10G speed.
- Waits for RX clock and PHY status signal to settle.
- Prints PHY status.
- Checks for another 10 valid data on 10G speed.
- Switches to 25G speed once all 10 valid data passes.
- Waits for RX clock and PHY status signal to settle.
- Prints PHY status.
- Checks for another 10 valid data on 25G speed.
- Analyzes the results. The successful testbench displays "Simulation PASSED." when the PTP delay and offset data is within the threshold value.
The following sample output illustrates a successful simulation test run:
# Running at 25G mode... # # # Waiting for RX alignment... # iatpg_pipeline_global_en is set # iatpg_pipeline_global_en is set # RX deskew locked. # RX lane aligmnent locked. # # Sending packets... # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000064457 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000064bb4 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000fffffffff8a2 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000643b5 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000520 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000634fb # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000063f3b # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000063a1a # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x00000000000000000006445a # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000063e95 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000648d5 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000643b5 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000520 # Offset within tolerence range. # # # # Finished sending packets. # # # # Switching to 10G mode: 10G Reconfig starts... # Switching to 10G mode: 10G Reconfig End. # # Waiting for RX alignment... # RX deskew locked. # RX lane aligmnent locked. # # Configuring 1588 period... # Configuring 1588 period done. # # Sending packets... # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000e5a7d # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000002013 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000e0764 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000ffffffff99a0 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000e0764 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000ffffffffa66d # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000dfa97 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000006660 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000e1431 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000005993 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000e2db7 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000ffffffffccc0 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000e1431 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000ffffffff8006 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000e60e4 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000fffffffff320 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000dfa97 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000005993 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000e874b # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000ce0 # Offset within tolerence range. # # # # Finished sending packets. # # # # Switching to 25G mode: 25G Reconfig start... # Switching to 25G mode: 25G Reconfig end. # # Waiting for RX alignment... # RX deskew locked. # RX lane aligmnent locked. # # Configuring 1588 period... # Configuring 1588 period done. # # Sending packets... # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000063c58 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000063c58 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x00000000000000000006502f # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x00000000000000000006502f # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x00000000000000000006554d # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000064b10 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000064b10 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000064bb4 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000064bb4 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000065a6c # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # # Finished sending packets. # # ** # ** Testbench complete. # **
2.5. Compilation
Follow the procedure in Compiling and Configuring the Design Example in Hardware to compile and configure the design example in the selected hardware.
You can estimate resource utilization and Fmax using the compilation-only design example. You can compile your design using the Start Compilation command on the Processing menu in the Intel® Quartus® Prime Pro Edition software. A successful compilation generates the compilation report summary.
For more information, refer to Design Compilation in the Compiler User Guide: Intel® Quartus® Prime Pro Edition .
2.6. Hardware Testing
Follow the procedure at the provided related information link to test the design example in the selected hardware.
2.6.1. Test Procedure—Design Example Without the IEEE 1588v2 Feature
- Perform data rate switching to 10G:
- In Intel® Quartus® Prime Pro Edition software, go to Tools > In-System Sources & Probes Editor tool to open the default source and probe GUI.
- Set the source bit[1] in source and probe to 1.
- Perform data rate switching to 25G:
- In Intel® Quartus® Prime Pro Edition software, go to Tools > In-System Sources & Probes Editor tool to open the default source and probe GUI.
- Set the source bit[1] in source and probe to 0.
- Perform system reset release after executing the data rate reconfiguration:
- Click Tools > In-System Sources & Probes Editor tool for the default Source and Probe GUI.
- Toggle the system reset signal (Source[0]) from 0 to 1 to apply the reset and return the system reset signal back to 0 to release the system from the reset state.
- Monitor the Probe signals and ensure that the status is valid.
- Run the following commands in the system console to start the serial loopback test:
Table 7. Command Parameters Parameter Description Example Usage chkphy_status <link num> Displays the clock frequencies and PHY lock status. % chkphy_status 0 # Check status of link 0 chkmac_stats <link num> Displays the values in the MAC statistics counters. % chkmac_stats 1 # Checks mac statistics counter of link 1 clear_all_stats <link num> Clears the IP core statistics counters. % clear_all_stats 1 # Clears statistics counter of link 1 start_gen <link num> Starts the packet generator. % start_gen 1 # Begin packet generation on link 1 stop_gen <link num> Stops the packet generator. % stop_gen 1 # Stop packet generation on link 1 loop_on <link num> Turns on internal serial loopback. % loop_on 2 # Turn on internal loopback on link 2 loop_off <link num> Turns off internal serial loopback. % loop_off 2 # Turn off internal loopback on link 2 reg_read <addr> Returns the IP core register value at <addr>. % reg_read 0x302 # Read IP CSR register at address 302 of link 0 % reg_read 0x4542 # Read transceiver reconfiguration register at address 4542 of link 0
reg_write <addr> <data> Writes <data> to the IP core register at address <addr>. % reg_write 0x30301 0x1 # Write 0x1 to IP CSR scratch register at address 301 of link 3 % reg_write 0x34542 0x0 # Write 0x0 to transceiver reconfiguration register at address 4542 of link 3
Note:- For single-channel design, <link num> is always 0.
- For multi-channel design, <link num> is the channel number. The valid channel number range is 0 to 3.
- Type loop_on <link num> to turn on the internal serial loopback mode.
- Type chkphy_status <link num> to check the status of the PHY. The TXCLK, RXCLK, and RX status should have the same values shown below for a stable link:Figure 11. System Console Example Printout
- Type clear_all_stats <link num> to clear TX and RX statistics registers.
- Type start_gen <link num> to begin packet generation.
- Type stop_gen <link num> to stop packet generation.
- Type chkmac_stats <link num> to read the TX and RX statistics counters. Make sure that:
- The transmitted packet frames match the received packet frames.
- No error frames are received.
- Type loop_off <link num> to turn off the internal serial loopback.
Note: The above configuration is applied to the default 25G mode for the first time.

2.6.2. Test Procedure—Design Example with the IEEE 1588v2 Feature
Follow these steps to test the design examples in hardware using PMA serial loopback:
- Perform data rate switching to 10G:
- In Intel® Quartus® Prime Pro Edition software, go to Tools > In-System Sources & Probes Editor tool to open the default source and probe GUI.
- Set the source bit[1] in source and probe to 1.
- In the System Console panel, type the following commands as below to set the correct clock period for the required TX and RX MAC clock frequency in 10G speed mode:
reg_write 0xA05 0x66666 reg_write 0xB05 0x66666
- Perform data rate switching to 25G:
- In Intel® Quartus® Prime Pro Edition software, go to Tools > In-System Sources & Probes Editor tool to open the default source and probe GUI.
- Set the source bit[1] in source and probe to 0.
- In the System Console panel, type the following commands as below to set the correct clock period for the required TX and RX MAC clock frequency in 25G speed mode:
reg_write 0xA05 0x28F5C reg_write 0xB05 0x28F5C
Note: 0xA05 is register that configure TX_PTP_CLK_PERIOD. 0xB05 is register that configure RX_PTP_CLK_PERIOD. - Perform system reset release after executing the data rate reconfiguration:
- Click Tools > In-System Sources & Probes Editor tool for the default Source and Probe GUI.
- Toggle the system reset signal (Source[0]) from 0 to 1 to apply the reset and return the system reset signal back to 0 to release the system from the reset state.
- Monitor the Probe signals and ensure that the status is valid.
- To perform internal serial loopback test, refer to the Test Procedure—Design Example Without the IEEE 1588v2 Feature section of this chapter.
3. 25G Ethernet Single-Channel Design Example for Intel Stratix 10 Devices
Generate the design example from the Example Design tab of the 25G Ethernet Intel® FPGA IP parameter editor. You can choose to generate the design with or without the IEEE 1588v2 feature. You can also choose to generate the design with or without the Reed-Solomon Forward Error Correction (RS-FEC) feature.
3.1. Features
- Supports single Ethernet channel operating at 25G.
- Generates design example with IEEE 1588v2 feature.
- Generates design example with RS-FEC feature.
- Generates design example separately from Intel® Stratix® 10 Transceiver Native PHY.
- Provides testbench and simulation script.
3.2. Hardware and Software Requirements
- Intel® Quartus® Prime Pro Edition software.
- ModelSim* -SE, NCSim (Verilog only), VCS* , and Xcelium* simulator.
- Intel® Stratix® 10 GX Signal Integrity L-Tile (Production) Development Kit (1SX280LU2F50E1VG) for hardware testing.
3.3. Functional Description
The 25G Ethernet single-channel design example consists of two core variants—MAC+PCS+PMA and MAC+PCS. The following block diagrams show the design components and the top-level signals of the two core variants in the 25G Ethernet single-channel design example.
3.3.1. Design Components
Component | Description |
---|---|
25G Ethernet Intel® FPGA IP |
Consists of MAC, PCS, and Transceiver PHY, with the following configuration:
For the design example with the IEEE 1588 feature, the following additional parameters are configured:
For the design example with the RS-FEC feature, the following additional parameter is configured:
|
ATX PLL | Generates TX serial clocks for the 25G transceiver. |
Client logic | Consists of:
|
Source and Probe | Source and probe signals, including system reset input signal, which you can use for debugging. |
Design Components for the IEEE 1588v2 Feature | |
Sampling PLL | Generates the clocks for the IEEE 1588v2 design components.
|
Time-of-day (ToD) Sync | Synchronizes the 25G ToD. |
ToD Tx | ToD for transmit paths for the 25G transceiver. |
ToD Rx | ToD for receive paths for the 25G transceiver. |
Master Precision Time Protocol (PTP) | Master PTP consists of a packet generator and a packet receiver.
|
Slave PTP | Slave PTP consists of a packet generator, a packet receiver, and a packet compute.
|
3.4. Simulation
3.4.1. Testbench
Component | Description |
---|---|
Device under test (DUT) | The 25G Ethernet Intel® FPGA IP core. |
Reconfiguration Sequencer | Reconfigures the transceiver channel speed from 10 Gbps to 25 Gbps, and vice versa. |
Ethernet Packet Generator and Packet Monitor |
|
ATX PLL | Generates a TX serial clock for the Intel® Stratix® 10 10G/25G transceiver which is wrapped in the 25G Ethernet Intel® FPGA IP core. |
3.4.2. Simulation Design Example Components
File Name | Description |
---|---|
Testbench and Simulation Files | |
basic_avl_tb_top.v | Top-level testbench file. The testbench instantiates the DUT, performs Avalon® memory-mapped configuration on design components and client logic, and sends and receives packet to or from the 25G Ethernet Intel® FPGA IP. |
Testbench Scripts | |
run_vsim.do | The ModelSim script to run the testbench. |
run_vcs.sh | The Synopsys VCS* script to run the testbench. |
run_ncsim.sh | The Cadence NCSim script to run the testbench. |
run_xcelium.sh | The Xcelium* script to run the testbench. |
3.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature
The simulation test case performs the following actions:
- Instantiates and ATX PLL.
- Waits for RX clock and PHY status signal to settle.
- Prints PHY status.
- Analyzes the results. The successful testbench sends ten packets, receives ten packets, and displays "Testbench complete."

3.4.4. Test Case—Design Example with the IEEE 1588v2 Feature
The simulation test case performs the following actions:
- Instantiates , ATX PLL, and IO PLL (sampling PLL).
- Waits for RX clock and PHY status signal to settle.
- Prints PHY status.
- Checks for 10 valid data.
- Analyzes the results. The successful testbench displays "Testbench complete." when the PTP delay and offset data are within the threshold values.
The following sample output illustrates a successful simulation test run:
# # Waiting for RX alignment... # iatpg_pipeline_global_en is set # iatpg_pipeline_global_en is set # RX deskew locked. # RX lane aligmnent locked. # # Sending packets... # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000064457 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000064bb4 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000fffffffff8a2 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000643b5 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000520 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000634fb # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000063f3b # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000063a1a # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x00000000000000000006445a # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000063e95 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000648d5 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000 # Offset within tolerence range. # # # Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000643b5 # Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000520 # Offset within tolerence range. # # # # Finished sending packets. # # ** # ** Testbench complete. # **


3.5. Compilation
Follow the procedure in Compiling and Configuring the Design Example in Hardware to compile and configure the design example in the selected hardware.
You can estimate resource utilization and Fmax using the compilation-only design example. You can compile your design using the Start Compilation command on the Processing menu in the Intel® Quartus® Prime Pro Edition software. A successful compilation generates the compilation report summary.
For more information, refer to Design Compilation in the Compiler User Guide: Intel® Quartus® Prime Pro Edition .
3.6. Hardware Testing
Follow the procedure at the provided related information link to test the design example in the selected hardware.
3.6.1. Test Procedure—Design Example With and Without the IEEE 1588v2 Feature
Follow these steps to test the design example in hardware:
- Before you run the hardware testing for this design example, you must reset the system:
- Click Tools > In-System Sources & Probes Editor tool for the default Source and Probe GUI.
- Toggle the system reset signal (Source[0]) from 0 to 1 to apply the reset and return the system reset signal back to 0 to release the system from the reset state.
- Monitor the Probe signals and ensure that the status is valid.
- To perform internal serial loopback test, refer to the Test Procedure—Design Example Without the IEEE 1588v2 Feature section of the 10G/25G Ethernet Single-Channel Design Example for Intel® Stratix® 10 Devices chapter.
4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices
Generate the design example from the Example Design tab of the 25G Ethernet Intel® FPGA IP parameter editor.
4.1. Features
- Supports up to four Ethernet channels operating at 25G.
- Provides testbench and simulation script.
4.2. Hardware and Software Requirements
- Intel® Quartus® Prime Pro Edition software.
- ModelSim* -SE, NCSim (Verilog only), VCS* , and Xcelium* simulator.
- Intel® Stratix® 10 GX Signal Integrity L-Tile (Production) Development Kit (1SX280LU2F50E1VG) for hardware testing.
4.3. Functional Description
The 25G Ethernet multi-channel design example consists of various components. The following block diagram shows the design components and the top-level signals of the design example.
4.3.1. Design Components
Component | Description |
---|---|
25G Ethernet Intel® FPGA IP |
Consists of MAC, PCS, and Transceiver PHY, with the following configuration:
|
ATX PLL | Generates TX serial clocks for the 25G transceiver. |
Client logic | Consists of:
|
Source and Probe | Source and probe signals, including system reset input signal, which you can use for debugging. |
4.4. Simulation
4.4.1. Testbench
Component | Description |
---|---|
Device under test (DUT) | The 25G Ethernet Intel® FPGA IP core. |
Reconfiguration Sequencer | Reconfigures the transceiver channel speed from 10 Gbps to 25 Gbps, and vice versa. |
Ethernet Packet Generator and Packet Monitor |
|
ATX PLL | Generates a TX serial clock for the Intel® Stratix® 10 10G/25G transceiver which is wrapped in the 25G Ethernet Intel® FPGA IP core. |
4.4.2. Simulation Design Example Components
File Name | Description |
---|---|
Testbench and Simulation Files | |
basic_avl_tb_top.v | Top-level testbench file. The testbench instantiates the DUT, performs Avalon® memory-mapped configuration on design components and client logic, and sends and receives packet to or from the 25G Ethernet Intel® FPGA IP. |
Testbench Scripts | |
run_vsim.do | The ModelSim script to run the testbench. |
run_vcs.sh | The Synopsys VCS* script to run the testbench. |
run_ncsim.sh | The Cadence NCSim script to run the testbench. |
run_xcelium.sh | The Xcelium* script to run the testbench. |
4.4.3. Test Case
The simulation test case performs the following steps:
- Instantiates 25G Ethernet Intel® FPGA IP and ATX PLL.
- Waits for PHY status signal to settle.
- Prints PHY status.
- Analyzes the results. The successful testbench sends and receives packets, and displays "Testbench complete."



4.5. Compilation
Follow the procedure in Compiling and Configuring the Design Example in Hardware to compile and configure the design example in the selected hardware.
You can estimate resource utilization and Fmax using the compilation-only design example. You can compile your design using the Start Compilation command on the Processing menu in the Intel® Quartus® Prime Pro Edition software. A successful compilation generates the compilation report summary.
For more information, refer to Design Compilation in the Compiler User Guide: Intel® Quartus® Prime Pro Edition .
4.6. Hardware Testing
Follow the procedure at the provided related information link to test the design example in the selected hardware.
4.6.1. Test Procedure
Follow these steps to test the design example in hardware:
- Before you run the hardware testing for this design example, you must reset the system:
- Click Tools > In-System Sources & Probes Editor tool for the default Source and Probe GUI.
- Toggle the system reset signal (Source[0]) from 0 to 1 to apply the reset and return the system reset signal back to 0 to release the system from the reset state.
- Monitor the Probe signals and ensure that the status is valid.
- To perform internal serial loopback test, refer to the Test Procedure—Design Example Without the IEEE 1588v2 Feature section of the 10G/25G Ethernet Single-Channel Design Example for
Intel®
Stratix® 10 Devices chapter.Note: link_num is valid for 0 to 3 only.
5. 25G Ethernet Intel FPGA IP Design Example References
5.1. Design Example Interface Signals
The 25G Ethernet Intel® FPGA IP core testbench is self-contained and does not require you to drive any input signals.
Signal | Direction | Comments |
---|---|---|
clk100 | Input |
Drive at 100 MHz. The intent is to drive this from a 100 Mhz oscillator on the board. |
clk_ref | Input | Drive at 644.53125 MHz or 322.265625 MHz from an oscillator on the board. |
cpu_resetn | Input | Resets the IP core. Active low. Drives the global hard reset csr_reset_n to the IP core. |
tx_serial | Output | Transceiver PHY output serial data. |
rx_serial | Input | Transceiver PHY input serial data. |
user_led[7:0] | Output | Status signals. The hardware design example connects
these bits to drive LEDs on the target board. Individual bits
reflect the following signal values and clock behavior:
|
5.2. Design Example Registers
Word Offset |
Register Category |
---|---|
Variant: Single-Channel | |
0X0000–0X0DFF | Register range to access the Status Registers. |
0X4000–0X7FFF | Register range to access the Reconfiguration Registers. |
0X10000–0X10001 | Register range to access the Reconfiguration Registers module for 10G/25G switching. |
0x1020 | 32-bit average_offset_fnsec_r register:
|
0x1021 | 32-bit average_offset_fnsec_to_mem register:
|
0x1030 | 32-bit average_delay_fnsec_r register:
|
0x1031 | 32-bit average_delay_fnsec_to_mem register:
|
Variant: Multi-Channel | |
0x00000–0x30DFF | For multi-channel design examples, the base address of all channels are incremented with 0x10000. This corresponds to:
|
0x04000-0x37FFF | For multi-channel design examples, the base address of all channels are incremented with 0x10000. This corresponds to:
|
- For Intel® Stratix® 10 H-tile production device, disable the background calibration prior to accessing the transceiver core reconfiguration register, as described in the Disabling Background Calibration section of the 25G Ethernet Intel® FPGA IP User Guide.
- Dynamic reconfiguration switching for 10G/25G is not available for multi-channel designs.
- For single-channel design example, 0x4000 is the base address of the PHY registers. For example, to read the background calibration register, type reg_read 0x4542.
- For multi-channel design example, the base address of the PHY registers is 0x4000 + (0x10000 * <link num>). For example, to read the background calibration register at channel 2, type reg_read 0x24542.
5.3. Using Transceiver Toolkit on H-Tile Production Device
If your design example targets the H-tile production device and Enable auto adaptation triggering for RX PMA CTLE/DFE mode option is turned on, you must perform additional steps to configure the register 0x343 bit[0] before you can use the Transceiver Toolkit. Refer to the description for register 0x343 in the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide for more information.
- Follow the procedure in the Testing the 25G Ethernet Intel® FPGA IP Design in Hardware section to load the main.tcl script.
- For single-channel design example, type reg_write 0x343 0x1 to hold the auto adaptation module FSM in idle state.
- For multi-channel design example,
- type reg_write 0x343 0x1 for channel 0
- type reg_write 0x10343 0x1 for channel 1
- type reg_write 0x20343 0x1 for channel 2
- type reg_write 0x30343 0x1 for channel 3
- Launch the Transceiver Toolkit.
- Close the Transceiver Toolkit.
- For single-channel design example, type reg_write 0x343 0x0 to re-start the auto adaptation module FSM.
- For multi-channel design example,
- type reg_write 0x343 0x0 for channel 0
- type reg_write 0x10343 0x0 for channel 1
- type reg_write 0x20343 0x0 for channel 2
- type reg_write 0x30343 0x0 for channel 3
6. 25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
Intel® Quartus® Prime Version | IP Core Version | User Guide |
---|---|---|
19.1 | 19.1 | 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide |
18.1 | 18.1 | 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide |
18.0 | 18.0 | 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide |
7. Document Revision History for the 25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide
Document Version | Intel® Quartus® Prime Version | IP Version | Changes |
---|---|---|---|
2020.06.18 | 19.2 | 19.2.0 |
|
2020.04.13 | 19.2 | 19.2.0 | Added new topic—Using Transceiver Toolkit on H-Tile Production Device. |
2020.02.14 | 19.2 | 19.2.0 | Updated the procedure steps in the Changing Target Device in Hardware Design Example section. |
2019.12.13 | 19.2 | 19.2.0 | Updated the procedure steps in the Changing Target Device in Hardware Design Example section. |
2019.08.29 | 19.2 | 19.2.0 | Updated the instruction for the ModelSim* simulator in Table: Steps to Simulate the Testbench. |
2019.07.01 | 19.2 | 19.2.0 |
|
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2019.05.10 | 19.1 |
|
2019.01.07 | 18.1 |
|
2018.10.03 | 18.1 |
|
2018.06.25 | 18.0 | Initial release. |