AN 690: PCI Express* Avalon® -MM DMA Reference Design

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ID 683824
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. AN 690: PCI Express Avalon-MM DMA Reference Design
1. AN 690: PCI Express Avalon-MM DMA Reference Design x
1.1. Deliverables Included with the Reference Design 1.2. Reference Design Functional Description 1.3. Avalon-MM DMA 1.4. Reference Design 1.5. DMA Operation Flow 1.6. Running the Reference Design 1.7. Understanding PCI Express Throughput 1.8. Document Revision History for AN-690
1.2. Reference Design Functional Description x
1.2.1. Parameter Settings
1.6. Running the Reference Design x
1.6.1. Installing the Driver and Application 1.6.2. Installing the Windows Software 1.6.3. Installing the Hardware 1.6.4. Running the Software 1.6.5. Peak Throughput
1.7. Understanding PCI Express Throughput x
1.7.1. Throughput for Posted Writes 1.7.2. Throughput for Reads
1.7.1. Throughput for Posted Writes x
1.7.1.1. Specifying the Maximum Payload Size
1. AN 690: PCI Express Avalon-MM DMA Reference Design

1.7.1. Throughput for Posted Writes

The theoretical maximum throughput calculation uses the following formula: 

Throughput  = payload size / (payload size + overhead) * link data rate

Figure 5. Maximum Throughput for Memory Writes The graph shows the maximum throughput with different TLP header and payload sizes. The DLLPs and PLPs are excluded from this calculation. For a 256-byte maximum payload size and a 3-dword header the overhead is five dwords. Because the interface is 256 bits, the 5-dword header requires a single bus cycle. The 256-byte payload requires 8 bus cycles.
The following equation shows maximum theoretical throughput: 
Maximum throughput = 8 cycles/9 cycles  = 88.88% * 8 GBps = 7.2 GBps

Section Content
Specifying the Maximum Payload Size

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