AN 690: PCI Express* Avalon® -MM DMA Reference Design

Download
ID 683824
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. AN 690: PCI Express Avalon-MM DMA Reference Design
1. AN 690: PCI Express Avalon-MM DMA Reference Design x
1.1. Deliverables Included with the Reference Design 1.2. Reference Design Functional Description 1.3. Avalon-MM DMA 1.4. Reference Design 1.5. DMA Operation Flow 1.6. Running the Reference Design 1.7. Understanding PCI Express Throughput 1.8. Document Revision History for AN-690
1.2. Reference Design Functional Description x
1.2.1. Parameter Settings Quartus® Prime Settings
1.6. Running the Reference Design x
1.6.1. Installing the Driver and Application 1.6.2. Installing the Windows Software 1.6.3. Installing the Hardware 1.6.4. Running the Software 1.6.5. Peak Throughput
1.7. Understanding PCI Express Throughput x
1.7.1. Throughput for Posted Writes 1.7.2. Throughput for Reads
1.7.1. Throughput for Posted Writes x
1.7.1.1. Specifying the Maximum Payload Size
1. AN 690: PCI Express Avalon-MM DMA Reference Design

1.2.1. Parameter Settings

The Hard IP for PCI Express variant used in this reference design supports a 256-byte maximum payload size. The following tables list the values for all parameters.

Table 1.   System Settings

Parameter

Value

Number of lanes

Arria® 10 , Stratix® V, and Stratix 10 : x8

Arria V and Cyclone V® : x4

Lane rate

Arria® 10 , Stratix® V, and Stratix 10 : Gen3

Arria V and Cyclone V® : Gen2

RX buffer credit allocation – performance for received request

Arria V , Arria 10 , Cyclone V, and Stratix® V : Low

Stratix 10: Not available

Reference clock frequency

100 MHz

Enable configuration via the PCIe link

Disable

Use ATX PLL

Disable

Table 2.   Base Address Register (BAR) Settings

Parameter

Value

BAR0 Type

64-bit prefetchable memory

BAR0 Size

64 KB – 16 bits

BAR4 Type 64-bit prefetchable
BAR4 size 64 KB – 16 bits

BAR1-3, BAR5

Disable

Table 3.  Device Identification Register Settings

Parameter

Value

Vendor ID

0x00001172

Device ID

0x0000E003

Revision ID

0x00000001

Class Code

0x00000000

Subsystem Vendor ID

0x00000000

Subsystem Device ID

0x00002861

Table 4.   PCI Express/PCI Capabilities

Parameter

Value

Maximum payload size

256 Bytes

Completion timeout range

ABCD

Implement Completion Timeout Disable

Enable

Table 5.   Error Reporting Settings

Parameter

Value

Advanced error reporting (AER)

Disable

ECRC checking

Disable

ECRC generation

Disable

Table 6.  Link Settings

Parameter

Value

Link port number

1

Slot clock configuration

Enable

Table 7.  MSI and MSI-X Settings

Parameter

Value

Number of MSI messages requested

4

Implement MSI-X

Disable

Table size

0

Table offset

0x0000000000000000

Table BAR indicator

0

Pending bit array (PBA) offset

0x0000000000000000

PBA BAR Indicator

0

Table 8.  Power Management

Parameter

Value

Endpoint L0s acceptable latency

Maximum of 64 ns

Endpoint L1 acceptable latency

Maximum of 1 us

Table 9.   PCIe Address Space Setting

Parameter

Value

Address width of accessible PCIe memory space

32

Quartus® Prime Settings

The Quartus Prime Archive File (*.qar) file in the reference design package has the recommended synthesis, fitter, and timing analysis settings for the parameters specified in this reference design.

Level Two Title

Did you find the information on this page useful?

Characters remaining:

Feedback Message