1.4. Reference Design
The reference design uses a 64-KB dual port memory in the FPGA in the FPGA fabric. The read DMA moves the data from the system memory to the 64-KB dual port memory. The write DMA moves the data from the 64-KB dual port memory to the system memory. Because this is a dual port memory, the read and the write DMA can access memory simultaneously.
|Avalon-MM DMA||pcie_256_dma||This is the 256-bit Avalon-MM with DMA module. It consists of two read and write data movers, a RX Avalon-MM master , a TX Avalon-MM slave, and an internal descriptor controller. This reference design uses an internal descriptor controller. You can also specify an external descriptor controller using the parameter editor.|
|RXM_BAR0||N/A||This is an Avalon-MM master port. It provides memory access to the PCIe host. The host programs the descriptor controller through this port Because this reference design uses an internal descriptor controller, the port connection is not shown in Platform Designer. The connection is made inside the Avalon-MM DMA module.|
|RXM_BAR4||Rxm_BAR4||This is an Avalon-MM master port. It provides memory access to the PCIe host. In the reference design, connects to one port of the 64-KB on-chip memory.
In a typical application, software controls this port to initialize the on-chip memory and read back the data to verify results.
|TX Avalon-MM Slave||Txs||This is an Avalon-MM slave port. In a typical application, an Avalon-MM master drives this por to send memory reads or writes to the PCIe domain.
The descriptor controller uses it to write DMA status back to descriptor data in the PCIe domain when the DMA completes. The descriptor controller also uses this port to send upstream MSI interrupts.
|Read Data Mover||dma_rd_master||This is an Avalon-MM master port.
The Read Data Mover moves data from the PCIe domain to the on-chip memory through port s2 during normal read DMA operations. The Read Data Mover also fetches the descriptors from the PCIe domain and writes them to the FIFO in the Descriptor Controller. The dma_rd_master port connects to the write DMA FIFO, wr_dts_slave, and read DMA FIFO, rd_dts_slave, ports.
|Write Data Mover||dma_wr_master||This is an Avalon-MM master port.
The Write Data Mover generates reads to read data from on-chip memory and then writes the data to a destination in PCIe domain. In this reference design, it uses another port to access the dual port on-chip memory.
|FIFO in Descriptor Controller||wr_dts_slave and rd_dts_slave||This is an Avalon-MM slave port for the FIFO in Descriptor Controller.
When the Read Data Mover fetches the descriptors from system memory, it writes the descriptors to the FIFO through this port.
Because there are two separate groups of descriptors for read and write, there are two ports available.
For the write DMA, the FIFO address range is 0x0801_2000 -0x0801_3FFF.
For the read DMA, the FIFO address range is 0x0801_0000 -0x0801_1FFF.
Software enumeration the DMA establishes these address.
|Control in Descriptor Controller||wr_dcm_master and rd_dcm_master|| The Descriptor Controller's control block has two transmit and receive ports. One for read DMA and another one for write DMA. The receive port connects to RXM_BAR0. The transmit port connects to Txs.
The receive path from RXM_BAR0 is connected internally, so it is not shown in the DMA Reference Design Platform Designer Connections figure. For the transmit path, both read and write DMA ports connect to the Txs externally. These ports appear in the DMA Reference Design Platform Designer Connections figure.
|64k-byte Dual Port RAM||Onchip_memory2_0|| This is a 64-KB dual port on-chip memory. The address range is 0x0800_0000- 0x0800_FFFF on the Avalon-MM bus. This address is the source address for write DMAs or destination address for read DMAs.
To prevent data corruption, software divides the memory into separate regions for reads and writes. The regions do not overlap.
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