F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 10/11/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.3. Simulation

The testbench provides basic functionality such as the startup and wait for lock and send and receive a few packets using the ROM-based packet generator.

You can enable the Fast Sim model to speed up the duration of your simulation. For more information, refer to Fast Sim Model for FGT Variants.

Figure 10.  F-Tile Ethernet Intel FPGA Hard IP Simulation Design Example Block Diagram

The following sections describe the simulation testbench flow variations based on the selected client interface.

Did you find the information on this page useful?

Characters remaining:

Feedback Message