F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 10/11/2021
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel FPGA Hard IP Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Generating Tile Files 1.4. Simulating the Design Example Testbench 1.5. Hardware and Software Requirements 1.6. Testing the Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.4. Simulating the Design Example Testbench x
1.4.1. Fast Sim Model for FGT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel FPGA Hard IP Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

4.5. Hardware Design Example

Follow these steps to test Ethernet-based design examples with enabled auto-negotiation and link training in hardware:
  1. Generate design example as described in Generating the Design.
  2. Modify the .qsf settings:
    • Set device to match the appropriate ordering part number (OPN) for your design.
    • Update the pinout to match the board and the design function.
    • Assign the appropriate VID settings in your .qsf file to match your board.
  3. Generate the .sof file.
  4. Update board clock settings. The default value for the PHY reference clock is 156.25 MHz. The default value for the reconfiguration clock is 100 MHz.
  5. Insert appropriate electrical loopback plug into the Ethernet port.
  6. Program the design.
  7. Open Tools > System Debugging Tools > System Console.
  8. Navigate to the hardware directory <design_example>/hardware_test_design/hwtest directory.
  9. Type source main_<variant_type>.tcl.
  10. Type set_jtag<number_of appropriate_JTAG_master>
  11. Perform this step if external loopback module is connected. Skip this step if the design connects to link partner.
    1. Type command to read the seq cfg register:
      reg_read 0x101002C0
    2. Type command to set the ingore nonce value to 1:
      reg_write 0x10100300 0x737d0281
    3. Type command to restart the AN sequencer:
      reg_write 0x101002c0 0x00002003
    4. Type command to read the debug status:
      reg_read 0x101003c0
      The link is up if the command returns value 1f0.
  12. Type the following command to check the PHY status:
    chkphy_status
  13. Type the command to start and stop the packet generator. The function sends 16 packets.
    start_pkt_gen
stop_pkt_gen
  14. Type the command to check the MAC status:
    chkmac_status
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