F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 10/11/2021
Public

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5. Design Example: Multiple IP Core Instantiation

The multiple IP core design example demonstrates the ability to instantiate same F-Tile Ethernet Intel FPGA Hard IP multiple times in your design.

The number of instantiated IP instances depends on the Ethernet mode. For more details, refer to . To generate the design example, you must first set the parameter values for the IP core variation you intend to generate in your end product. Generating the design example creates multiple copies of your IP core; the testbench design example uses this variation as the DUT. If your parameter values for the DUT don't match the parameter values in your end product, the design example you generate does not exercise the IP core variation you intend.

The multi IP core design example supports PTP feature for FGT PMA type.

The following IP parameter settings were used to generate this design example:
Table 14.  IP Parameters for 25G Ethernet Mode with 1 Lane Design ExampleTable specifies parameter settings used to generate this design example.
Selected IP Parameter Settings Value
IP Tab: General Options
PMA type FGT
Ethernet mode 25GE-1
Client interface MAC segmented
FEC mode

IEEE 802.3 RS(528,514) (CL91)

PMA reference frequency 156.25
System PLL frequency 805.664062
Example Design Tab: Available Example Designs
Select Design Multi instance of IP core

For more information about steps on how to generate a design example, refer to the Generating the Design Example.

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