F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 10/11/2021
Public

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2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA

This section displays F-Tile Ethernet Intel FPGA Hard IP block diagram when you select FHT for PMA type in the IP Parameter Editor. In the FHT PMA variation, a separate clock feeds the FHT PMA reference clock block.
Figure 9.  F-Tile Ethernet Intel FPGA Hard IP Simulation Design Example Block Diagram with FHT PMA

In this variation, the system PLL include additional FHL common PLL block.

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