F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 10/11/2021
Public

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1.3. Generating Tile Files

The Support-Logic Generation is a pre-synthesis step used to generate tile-related files required for simulation and hardware design. The tile generation is required for all F-tile based design simulations. You must complete this step before simulation.

Using Graphical User Interface:

  1. In the Intel® Quartus® Prime Pro Edition, navigate to the Compilation Dashboard window for your project overview.
  2. Click Support-Logic Generation.
Using command prompt window:
  1. At the command prompt, navigate to the hardware_test_design folder in your example design:
    cd <your_design_path>/hardware_test_design
  2. If you enabled auto-negotiation and link training, you must specify the pin assignments. Append the eth_f_hw.qsf file with the recommended pin location assignments described in QSF Assignments.
    Note: This step is required only when you enabled the AN/LT feature in the F-Tile Ethernet Intel FPGA Hard IP and instantiated the F-Tile Ethernet Intel® FPGA IP.
  3. Run the following command:
    quartus_tlg eth_f_hw
This step generates eth_f_hw_tiles files. The generated files are located in the <your_design>/hardware_test_design directory and contain the full netlist for simulation and synthesis.

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