1. HDMI Intel® FPGA IP Quick Reference
2. HDMI Overview
3. HDMI Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI Source
6. HDMI Sink
7. HDMI Parameters
8. HDMI Simulation Example
9. Registers
10. HDMI Intel® FPGA IP User Guide Archives
11. Document Revision History for the HDMI Intel® FPGA IP User Guide
4.3.1.1. Transceiver Native PHY (RX)
4.3.1.2. PLL Intel FPGA IP Cores
4.3.1.3. PLL Reconfig Intel FPGA IP Core
4.3.1.4. Multirate Reconfig Controller (RX)
4.3.1.5. Oversampler (RX)
4.3.1.6. DCFIFO
4.3.1.7. Sink Display Data Channel (DDC) & Status and Control Data Channel (SCDC)
4.3.1.8. Transceiver Reconfiguration Controller
4.3.1.9. VIP Bypass and Audio, Auxiliary and InfoFrame Buffers
4.3.1.10. Transceiver Native PHY (TX)
4.3.1.11. Transceiver PHY Reset Controller
4.3.1.12. Oversampler (TX)
4.3.1.13. Clock Enable Generator
4.3.1.14. Platform Designer System
5.1. Source Functional Description
5.2. Source Interfaces
5.3. Source Clock Tree
5.4. Link Training Procedure
5.5. FRL Clocking Scheme
5.6. Valid Video Data
5.7. Source Deep Color Implementation When Support FRL = 0
5.8. Source Deep Color Implementation When Support FRL = 1
5.9. Variable Refresh Rate (VRR) and Auto Low Latency Mode (ALLM)
5.1.1. Source Scrambler, TMDS/TERC4 Encoder
5.1.2. Source Video Resampler
5.1.3. Source Window of Opportunity Generator
5.1.4. Source Auxiliary Packet Encoder
5.1.5. Source Auxiliary Packet Generators
5.1.6. Source Auxiliary Data Path Multiplexers
5.1.7. Source Auxiliary Control Port
5.1.8. Source Audio Encoder
5.1.9. HDCP 1.4 TX Architecture
5.1.10. HDCP 2.3 TX Architecture
5.1.11. FRL Packetizer
5.1.12. FRL Character Block and Super Block Mapping
5.1.13. Reed-Solomon (RS) Forward Error Correction (FEC) Generation and Insertion
5.1.14. FRL Scrambler and Encoder
5.1.15. Source FRL Resampler
5.1.16. TX Core-PHY Interface
5.1.17. I2C Controller
5.1.18. Pixel Repetition
5.1.19. AXI4-Stream to Clocked Video Converter (AXI2CV)
5.1.20. AXI4-Stream to Clocked Video Converter (AXI2CV) Remap
5.1.21. Avalon Memory-Mapped Demultiplexer
5.1.22. HDMI TX Register
5.1.23. HDMI TX Interrupt
5.1.24. TX AXI4-Stream Auxiliary Bridge
5.1.25. TX Auxiliary User Packet
5.1.26. TX AXI4-Stream Auxiliary Arbiter
5.1.27. TX AXI4-Stream Auxiliary Packetizer
5.1.28. TX Avalon-ST Auxiliary Arbiter
6.1.1. Sink Word Alignment and Channel Deskew
6.1.2. Sink Descrambler, TMDS/TERC4 Decoder
6.1.3. Sink Auxiliary Decoder
6.1.4. Sink Auxiliary Packet Capture
6.1.5. Sink Video Resampler
6.1.6. Sink Auxiliary Data Port
6.1.7. Sink Audio Decoder
6.1.8. Status and Control Data Channel (SCDC) Interface
6.1.9. HDCP 1.4 RX Architecture
6.1.10. HDCP 2.3 RX Architecture
6.1.11. FRL Depacketizer
6.1.12. Sink FRL Character Block and Super Block Demapper
6.1.13. Sink FRL Descrambler and Decoder
6.1.14. Sink FRL Resampler
6.1.15. RX Core-PHY Interface
6.1.16. I2C Target
6.1.17. I2C and EDID RAM Blocks
6.1.18. Pixel De-repetition
6.1.19. Clocked Video to AXI4-Stream (CV2AXI) Remap
6.1.20. Clocked Video to AXI4-Stream Converter (CV2AXI)
6.1.21. Avalon Memory-Mapped Demultiplexer
6.1.22. HDMI RX Register
6.1.23. HDMI RX Interrupt
6.1.24. RX AXI4-Stream Auxiliary Bridge
6.1.25. RX Auxiliary Packet Filter
6.1.26. RX Auxiliary User Packetizer
6.1.27. Variable Refresh Rate(VRR) and Auto Low Latency Mode (ALLM)
9.1.1.1. STATUS_CONTROL (0x00)
9.1.1.2. IRQ_STATUS (0x01)
9.1.1.3. IRQ_MASK (0x02)
9.1.1.4. VIDEO_FORMAT (0x03)
9.1.1.5. AVI_CONTROL (0x08)
9.1.1.6. AVI_PACKET_DATA0 (0x09)
9.1.1.7. AVI_PACKET_DATA1 (0x0A)
9.1.1.8. AVI_PACKET_DATA2 (0x0B)
9.1.1.9. AVI_PACKET_DATA3 (0x0C)
9.1.1.10. VSI_CONTROL (0x0D)
9.1.1.11. VSI_PACKET_HEADER (0x0E)
9.1.1.12. VSI_PACKET_DATA0 (0x0F)
9.1.1.13. VSI_PACKET_DATA1 (0x10)
9.1.1.14. USER_PACKET_STATUS_CONTROL (0x12)
9.1.1.15. USER_PACKET_HEADER (0x013)
9.1.1.16. USER_PACKET_DATA0 (0x014)
9.1.1.17. USER_PACKET_DATA1 (0x015)
9.1.1.18. USER_PACKET_DATA2 (0x016)
9.1.1.19. USER_PACKET_DATA3 (0x017)
9.1.1.20. USER_PACKET_DATA4 (0x018)
9.1.1.21. USER_PACKET_DATA5 (0x019)
9.1.1.22. USER_PACKET_DATA6 (0x01A)
9.1.1.23. USER_PACKET_DATA7 (0x01B)
9.1.1.24. AUDIO_INFOFRAME_CONTROL (0x20)
9.1.1.25. AUDIO_INFOFRAME_PACKET_DATA0 (0x21)
9.1.1.26. AUDIO_INFOFRAME_PACKET_DATA1 (0x22)
9.1.1.27. AUDIO_METADATA_CONTROL (0x24)
9.1.1.28. AUDIO_METADATA_PACKET_HEADER (0x025)
9.1.1.29. AUDIO_METADATA_PACKET_DATA0 (0x026)
9.1.1.30. AUDIO_METADATA_PACKET_DATA1 (0x027)
9.1.1.31. AUDIO_METADATA_PACKET_DATA2 (0x028)
9.1.1.32. AUDIO_METADATA_PACKET_DATA3 (0x029)
9.1.1.33. AUDIO_METADATA_PACKET_DATA4 (0x02A)
9.1.1.34. AUDIO_METADATA_PACKET_DATA5 (0x02B)
9.1.1.35. SCDC_FRL_CONTROL (0x031)
9.2.2.1. STATUS (0x50)
9.2.2.2. VIDEO_MODE_MATCH (0x51)
9.2.2.3. VIDEO_MODE_BANK_SELECT (0x53)
9.2.2.4. VIDEO_MODE_CONTROL (0x54)
9.2.2.5. VIDEO_MODE_SAMPLE_COUNT(0x55)
9.2.2.6. VIDEO_MODE_F0_LINE_COUNT (0x56)
9.2.2.7. VIDEO_MODE_F1_LINE_COUNT (0x57)
9.2.2.8. VIDEO_MODE_HORIZONTAL_FRONT_PORCH (0x58)
9.2.2.9. VIDEO_MODE_HORIZONTAL_SYNC_LENGTH (0x59)
9.2.2.10. VIDEO_MODE_HORIZONTAL_BLANKING (0x5A)
9.2.2.11. VIDEO_MODE_VERTICAL_FRONT_PORCH (0x5B)
9.2.2.12. VIDEO_MODE_VERTICAL_SYNC_LENGTH (0x5C)
9.2.2.13. VIDEO_MODE_VERTICAL_BLANKING (0x5D)
9.2.2.14. VIDEO_MODE_F0_VERTICAL_FRONT_PORCH (0x5E)
9.2.2.15. VIDEO_MODE_F0_VERTICAL_SYNC_LENGTH (0x5F)
9.2.2.16. VIDEO_MODE_F0_VERTICAL_BLANKING (0x60)
9.2.2.17. VIDEO_MODE_ACTIVE_PICTURE_LINE (0x61)
9.2.2.18. VIDEO_MODE_F0_VERTICAL_RISING (0x62)
9.2.2.19. VIDEO_MODE_FIELD_RISING (0x63)
9.2.2.20. VIDEO_MODE_FIELD_FALLING (0x64)
9.2.2.21. VIDEO_MODE_HORIZONTAL_SYNC_POLARITY (0x6B)
9.2.2.22. VIDEO_MODE_VERTICAL_SYNC_POLARITY (0x6C)
9.2.2.23. VIDEO_MODE_VALID (0x6D)
9.3.1.1. STATUS (0x01)
9.3.1.2. IRQ_STATUS (0x02)
9.3.1.3. IRQ_MASK (0x03)
9.3.1.4. HOTPLUG (0x04)
9.3.1.5. LINK_MODE (0x05)
9.3.1.6. VIDEO_COLOR (0x06)
9.3.1.7. AVI_PACKET_DATA0 (0x0C)
9.3.1.8. AVI_PACKET_DATA1 (0x0D)
9.3.1.9. AVI_PACKET_DATA2 (0x0E)
9.3.1.10. AVI_PACKET_DATA3 (0x0F)
9.3.1.11. USER_PACKET_FILTER (0x10)
9.3.1.12. USER_BUFFER_STATUS_CONTROL (0x11)
9.3.1.13. USER_BUFFER_LEVEL (0x12)
9.3.1.14. USER_BUFFER_DATA (0x13)
9.3.1.15. AUX_PACKET_FILTER (0x14)
9.3.1.16. AUDIO_INFOFRAME_PACKET_DATA0 (0x21)
9.3.1.17. AUDIO_INFOFRAME _PACKET_DATA1 (0x22)
9.3.1.18. AUDIO_METADATA _PACKET_HEADER (0x25)
9.3.1.19. AUDIO_METADATA _PACKET_DATA0 (0x26)
9.3.1.20. AUDIO_METADATA _PACKET_DATA1 (0x27)
9.3.1.21. AUDIO_METADATA _PACKET_DATA2 (0x28)
9.3.1.22. AUDIO_METADATA _PACKET_DATA3 (0x29)
9.3.1.23. AUDIO_METADATA _PACKET_DATA4 (0x2A)
9.3.1.24. AUDIO_METADATA _PACKET_DATA5 (0x2B)
9.3.1.25. VSI_PACKET_DATA0 (0x2C)
9.3.1.26. VSI_PACKET_DATA1 (0x2D)
9.3.1.27. SCDC_FRL_STATUS (0x2E)
9.3.1.28. SCDC_FRL_CONTROL (0x2F)
4.3.1.14.1. VIP Passthrough for HDMI Video Stream
For certain example designs, you can loop the video data output and synchronization signals from HDMI RX core through the VIP data path.
The Clocked Video Input II (CVI II) Intel® FPGA IP core converts clocked video formats to Avalon-ST video by stripping incoming clocked video of horizontal and vertical blanking, leaving only active picture data.
- The IP core provides clock crossing capabilities to allow video formats running at different frequencies to enter the system.
- The IP core also detects the format of the incoming clocked video and provides this information in a set of registers.
- The Nios II processor uses this information to reconfigure the video frame mode registers of the CVO IP core in the VIP passthrough design.
The Video Frame Buffer II Intel® FPGA IP core buffers video frames into external RAM.
- The IP core supports double and triple buffering with a range of options for frame dropping and repeating.
- You can use the buffering options to solve throughput issues in the data path and perform simple frame rate conversion.
In a VIP passthrough design, you can reference the HDMI source PLL and sink PLL using separate clock sources. However, in a VIP bypass design, you must reference the HDMI source PLL and sink PLL using the same clock source.
The Clocked Video Output II (CVO II) Intel® FPGA IP core converts data from the flow-controlled Avalon-ST video protocol to clocked video.
- The IP core provides clock crossing capabilities to allow video formats running at different frequencies to be created from the system.
- It formats the Avalon-ST video into clocked video by inserting horizontal and vertical blanking and generating horizontal and vertical synchronization information using the Avalon-ST video control and active picture packets.
- The video frame is described using the mode registers that are accessed through the Avalon-MM control port.
VIP Passthrough Design | VIP Bypass Design |
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Device Family | Symbols Per Clock | HDMI Specification Support | Bitec HDMI HSMC 2.0 Daughter Card | Directory | VIP Passthrough | VIP Bypass |
---|---|---|---|---|---|---|
Arria V | 2 | 1.4b | HSMC (Rev8) | av_sk | Supported | Supported |
4 | 2.0b | HSMC (Rev8) | av_sk_hdmi2 | Not supported | Supported | |
Stratix V | 2 | 2.0b | HSMC (Rev8) | sv_hdmi2 | Not supported | Supported |