HDMI Intel® FPGA IP User Guide

ID 683798
Date 12/04/2023
Public
Document Table of Contents

9.1.1.5. AVI_CONTROL (0x08)

Table 70.  AVI_CONTROL (0x08)
Name Bit(s) Access Description Reset
reserved 31:1
AVI disable 0 RW When set to 1, HDMI TX core does not send AVI infoframes from the AVI_PACKET_DATA registers When set to 0, HDMI TX core sends AVI infoframes from the AVI_PACKET_DATA registers 0x0