Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

ID 683763
Date 9/26/2022
Public
Document Table of Contents

5.3.1. Vendor Specific Capability Header Register

Table 6.  Vendor Specific Capability Header Register (Byte Offset: 0xD00)
Bits Name Reset Value Access Description
[15:0] PCI Express* Extended Capability ID 0x000B RO PCIe* specification defined value for VSEC Capability ID.
[19:16] Version 0x1 RO PCIe* specification defined value for VSEC version.
[31:20] Next Capability Offset Variable RO Starting address of the next Capability Structure implemented, if any.

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