Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

ID 683763
Date 9/26/2022
Public
Document Table of Contents

6.2.4. Setting Up and Compile the Updated Revision

Create a new revision to serve as the updated revision for the base design. The new revision uses a new core logic while re-uses the root partition exported from the base revision.

Follow these steps to create and compile an updated revision:

  1. On the Project menu, click Revisions. The Revisions window appears.
  2. To create a new revision, double-click <<new revision>>. The Create Revision window appears.
  3. In the Revision name: field, specify the revision name.
  4. In the Based on revision: field, select the base design.
  5. Enable This project uses a Partition Database (.qdb) file for the root partition box. In the Root Partition Database file:, select the root_partition.qdb generated from the base design.
    Note: This setting is also available in the Design Partitions window.
  6. In the Revision type: field, leave the option blank. The tool copies the type from the Based on revision: field.
  7. Click OK. The Intel® Quartus® Prime software exits the previous base design and loads the new design revision. The new design revision opens automatically. You can confirm the current revision by the Intel® Quartus® Prime software top tool bar menu.
  8. In the Design Partitions window, remove root_partition.qdb file from the Post Final Export File column.
  9. Create a new instance or module to replace or update the partition.
    For example, if you use <logic_name1> logic within the reserved core partition, and then change the <logic_name1> logic to <logic_name2> via entity rebinding, it replaced the <logic_name1> instance with the <logic_name2> instance.
  10. In the Design Partitions window, use the entity rebinding assignment to change the logic associated with the reserved core partition. Select the Entity Re-binding column when you use the entity rebinding assignment.
  11. In the Intel® Quartus® Prime software, click Assignments > Settings > Files and add <logic_name2>.v file. Remove the <logic_name1>.v file once you added <logic_name2>.v file.
  12. Verify the following lines in the .qsf file:
    set_instance_assignment -name ENTITY_REBINDING <logic_name2> \
    -to led_inst -entity top
  13. Click Processing > Start Compilation to run the design compilation.

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