Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

ID 683763
Date 9/26/2022
Public
Document Table of Contents

5.3.8. CvP Programming Control Register

Table 13.  CvP Programming Control Register (Byte Offset: 0xD2C)
Bits Name Reset Value Access Description
[31:2] 0x0000 RO Reserved.
[1] START_XFER 1'b0 RW Sets the CvP output to the FPGA control block indicating the start of a transfer.
[0] CVP_CONFIG 1'b0 RW When set to 1, the FPGA control block begins a transfer via CvP.

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