Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

ID 683763
Date 9/26/2022
Public
Document Table of Contents

3.2. Multiple Endpoints

Use the multiple endpoints topology to configure multiple FPGAs through a PCIe* switch. This topology provides you with the flexibility to select the device to be configured or update through the PCIe* link. You can connect any number of FPGAs to the host in this topology.

The PCIe* switch controls the core image configuration through the PCIe* link to the targeted PCIe* endpoint in the FPGA. You must ensure that the root port can respond to the PCIe* switch and direct the configuration transaction to the designated endpoint based on the bus/device/function address of the endpoint specified by the PCIe* switch.

Figure 4. Multiple Endpoints Topology

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