Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

ID 683763
Date 9/26/2022
Public
Document Table of Contents

3.1. Single Endpoint

Use the single endpoint topology to configure a single FPGA. In this topology, the PCIe* link connects one PCIe* endpoint in the FPGA device to one PCIe* root port in the host.

Figure 3. Single Endpoint Topology

Did you find the information on this page useful?

Characters remaining:

Feedback Message