Early Power Estimator for Intel® Cyclone® 10 LP FPGAs User Guide

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ID 683743
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Early Power Estimator for Intel® Cyclone® 10 LP 2. Setting Up the Early Power Estimator for Intel® Cyclone® 10 LP 3. Early Power Estimator Worksheets for Intel® Cyclone® 10 LP 4. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Cyclone® 10 LP
1. Overview of the Early Power Estimator for Intel® Cyclone® 10 LP x
1.1. Power Model Status 1.2. Document Revision History
2. Setting Up the Early Power Estimator for Intel® Cyclone® 10 LP x
2.1. System Requirements 2.2. Download and Install the Early Power Estimator 2.3. Estimating Power Consumption 2.4. Document Revision History
2.2. Download and Install the Early Power Estimator x
2.2.1. Changing the Macro Security Level in Microsoft Excel* 2003 2.2.2. Changing the Macro Security Level in Microsoft Excel* 2007 2.2.3. Changing the Macro Security Level in Microsoft Excel* 2010
2.3. Estimating Power Consumption x
2.3.1. Estimating Power Consumption Before Starting the FPGA Design 2.3.2. Estimating Power Consumption While Creating the FPGA Design 2.3.3. Estimating Power Consumption After Completing the FPGA Design
2.3.1. Estimating Power Consumption Before Starting the FPGA Design x
2.3.1.1. Entering Information into the Early Power Estimator 2.3.1.2. Manually Entering Values
2.3.2. Estimating Power Consumption While Creating the FPGA Design x
2.3.2.1. Importing a File 2.3.2.2. Generating the Early Power Estimator (EPE) File 2.3.2.3. Importing Data into the Early Power Estimator (EPE) Spreadsheet
3. Early Power Estimator Worksheets for Intel® Cyclone® 10 LP x
3.1. Cyclone® 10 LP EPE - Main Worksheet 3.2. Cyclone® 10 LP EPE - Logic Worksheet 3.3. Cyclone® 10 LP EPE - RAM Worksheet 3.4. Cyclone® 10 LP EPE - DSP Worksheet 3.5. Cyclone® 10 LP EPE - I/O Worksheet 3.6. Cyclone® 10 LP EPE - PLL Worksheet 3.7. Cyclone® 10 LP EPE - Clock Worksheet 3.8. Cyclone® 10 LP EPE - Report Worksheet 3.9. Cyclone® 10 LP EPE - Enpirion Worksheet 3.10. Document Revision History
3.1. Cyclone® 10 LP EPE - Main Worksheet x
3.1.1. Input Parameters 3.1.2. Thermal Power 3.1.3. Power Tree Design 3.1.4. Thermal Analysis
3.1.4. Thermal Analysis x
3.1.4.1. Not Using a Heat Sink 3.1.4.2. Using a Heat Sink
3.8. Cyclone® 10 LP EPE - Report Worksheet x
3.8.1. Static Power and Dynamic Current per Voltage Rail 3.8.2. Power Up Current 3.8.3. Power Breakout for Multiple Voltage Supplies 3.8.4. Power Regulator Settings
4. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Cyclone® 10 LP x
4.1. Toggle Rate 4.2. Airflow 4.3. Temperature 4.4. Heat Sink 4.5. Document Revision History
1. Overview of the Early Power Estimator for Intel® Cyclone® 10 LP
2. Setting Up the Early Power Estimator for Intel® Cyclone® 10 LP
3. Early Power Estimator Worksheets for Intel® Cyclone® 10 LP
4. Factors Affecting the Accuracy of the Early Power Estimator for Intel® Cyclone® 10 LP

3.1.2. Thermal Power

Thermal power is the power dissipated in the FPGA device. Total thermal power is a sum of the thermal power of all the resources used in the device, including the maximum power from standby and dynamic power.

Total thermal power includes only the thermal component for the I/O section and does not include the external power dissipation, such as from voltage-referenced termination resistors.

The static power (PSTATIC) is the thermal power dissipated on chip, independent of user clocks. PSTATIC includes the leakage power from all FPGA functional blocks, except for I/O DC bias power and transceiver DC bias power, which are accounted for in the I/O and transceiver sections.

PSTATIC is the only thermal power component which varies with junction temperature, selected device, and power characteristics (process).

The following figure shows the total thermal power (W) and PSTATIC consumed by the FPGA. The thermal power for each worksheet is displayed. To see how the thermal power for a worksheet was calculated, click on the button to view the selected worksheet.

Figure 2. Thermal Power Section in the Main Worksheet
Table 6.  Thermal Power Section Information
Column Heading Description
Logic This value shows the dynamic power consumed by adaptive logic modules (ALMs) and associated routing. To view details, click the Logic button.
RAM This value shows the dynamic power consumed by RAM blocks and associated routing. To view details, click the RAM button.
DSP This value shows the dynamic power consumed by digital signal processing (DSP) blocks and associated routing. To view details, click the DSP button.
I/O This value shows the thermal power consumed by I/O pins and associated routing. To view details, click the I/O button.
PLL This value shows the dynamic power consumed by phase-locked loops (PLLs). To view details, click the PLL button.
Clock This value shows the dynamic power consumed by clock networks. To view details, click the Clock button.
PSTATIC

This shows the thermal power dissipated on chip, independent of user clocks. This includes the leakage power from all FPGA functional blocks, except for I/O DC bias power and transceiver DC bias power.

PSTATIC is affected by junction temperature, selected device, and power characteristics.

Total FPGA This shows the total power dissipated as heat from the FPGA. This does not include power dissipated in off-chip termination resistors.
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