Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 1/04/2023
Document Table of Contents

11.3. Recommended Reset Sequence to Avoid Link Training Issues

  1. Wait until the FPGA is configured as indicated by the assertion of CONFIG_DONE from the FPGA block controller.
  2. Deassert the mgmt_rst_reset input to the Transceiver Reconfiguration Controller IP Core.
  3. Wait for tx_cal_busy and rx_cal_busy SERDES outputs to be deasserted.
  4. Deassert pin_perstn to take the Hard IP for PCIe out of reset. For plug-in cards, the minimum assertion time for pin_perstn is 100 ms. Embedded systems do not have a minimum assertion time for pin_perstn.

  5. Wait for thereset_status output to be deasserted
  6. Deassert the reset output to the Application Layer.