Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 1/04/2023
Document Table of Contents Channel Placement in Arria V Devices

Figure 47.  Arria V Gen1 and Gen2 Channel Placement Using the CMU PLLIn the following figures the channels shaded in blue provide the transmit CMU PLL generating the high-speed serial clock.

You can assign other protocols to unused channels the if data rate and clock specification exactly match the PCIe configuration.