Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 1/04/2023
Public
Document Table of Contents

8.1.6. Interrupts

The Hard IP for PCI Express offers the following interrupt mechanisms:

  • Message Signaled Interrupts (MSI)— MSI uses the Transaction Layer's request‑acknowledge handshaking protocol to implement interrupts. The MSI Capability structure is stored in the Configuration Space and is programmable using Configuration Space accesses.
  • MSI-X—The Transaction Layer generates MSI-X messages which are single dword memory writes. In contrast to the MSI capability structure, which contains all of the control and status information for the interrupt vectors, the MSI‑X Capability structure points to an MSI‑X table structure and MSI‑X PBA structure which are stored in memory.
  • Legacy interrupts—app_int_sts_vec[7:0] controls legacy interrupt generation. When asserted, the Hard IP to generates an Assert_INT<n> message TLP.

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