Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 1/04/2023
Document Table of Contents

6.1.1. MSI Interrupts

MSI interrupts are signaled on the PCI Express link using a single dword memory write TLP generated internally by the Arria V Hard IP for PCI Express. The app_msi_req input port controls MSI interrupt generation. When the input port asserts app_msi_req, it causes a MSI posted write TLP to be generated based on the MSI configuration register values and the app_msi_tc (traffic class) and app_msi_num (number) input ports. To enable MSI interrupts, software must first set the MSI enable bit and then disable legacy interrupts by setting the Interrupt Disable which is bit 10 of the Command register.

The following figure illustrates the architecture of the MSI handler block.

Figure 53. MSI Handler Block

The following figure illustrates a possible implementation of the MSI handler block with a per vector enable bit. A global Application Layer interrupt enable can also be implemented instead of this per vector MSI.

Figure 54. Example Implementation of the MSI Handler Block

There are 32 possible MSI messages. The number of messages requested by a particular component does not necessarily correspond to the number of messages allocated. For example, in the following figure, the Endpoint requests eight MSIs but is only allocated two. In this case, you must design the Application Layer to use only two allocated messages.

Figure 55. MSI Request Example

The following table describes three example implementations. The first example allocates all 32 MSI messages. The second and third examples only allocate 4 interrupts.

Table 62.  MSI Messages Requested, Allocated, and Mapped






System Error




Hot Plug and Power Management Event




Application Layer




MSI interrupts generated for Hot Plug, Power Management Events, and System Errors always use Traffic Class 0. MSI interrupts generated by the Application Layer can use any Traffic Class. For example, a DMA that generates an MSI at the end of a transmission can use the same traffic control as was used to transfer data.

The following figure illustrates the interactions among MSI interrupt signals for the Root Port. The minimum latency possible between app_msi_req and app_msi_ack is one clock cycle. In this timing diagram app_msi_req can extend beyond app_msi_ack before deasserting. However, app_msi_req must be deasserted before or within the same clock as app_msi_ack is deasserted to avoid inferring a new interrupt.

Figure 56. MSI Interrupt Signals Timing