Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 1/04/2023
Document Table of Contents

4.10.1. Configuration Space Register Access Timing

Figure 37. tl_cfg_ctl Timing

The following figure shows typical traffic on the tl_cfg_ctl bus. The tl_cfg_add index increments on the rising edge of the pld_clk. The address specifies which Configuration Space register data value is being driven onto tl_cfg_ctl.