Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 1/04/2023
Document Table of Contents

1.9. Performance and Resource Utilization

Because the PCIe protocol stack is implemented in hardened logic, it uses less than 1% of device resources.

Note: Soft calibration of the transceiver module requires additional logic. The amount of logic required depends on the configuration.