Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 1/04/2023
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15.6.9. BFM Configuration Procedures

The BFM configuration procedures are available in altpcietb_bfm_driver_rp.v. These procedures support configuration of the Root Port and Endpoint Configuration Space registers.

All Verilog HDL arguments are type integer and are input‑only unless specified otherwise.