HDMI Intel® Stratix 10 FPGA IP Design Example User Guide

ID 683701
Date 12/27/2022

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2. HDMI 2.1 Design Example (Support FRL = 1)

The HDMI 2.1 design example in FRL mode demonstrates one HDMI instance parallel loopback comprising four RX channels and four TX channels.
Table 6.   HDMI 2.1 Design Example for Intel® Stratix® 10 Devices
Design Example Data Rate Channel Mode Loopback Type

Stratix10 HDMI RX-TX Retransmit

  • 12 Gbps (FRL)
  • 10 Gbps (FRL)
  • 8 Gbps (FRL)
  • 6 Gbps (FRL)
  • 3 Gbps (FRL)
  • <6 Gbps (TMDS)
Simplex Parallel with FIFO buffer


  • The design instantiates FIFO buffers to perform a direct HDMI video stream passthrough between the HDMI 2.1 sink and source.
  • The design is capable to switch between FRL mode and TMDS mode during run time.
  • The design uses LED status for early debugging stage.
  • The design comes with HDMI RX and TX instances.
  • The design demonstrates the insertion and filtering of Dynamic Range and Mastering (HDR) InfoFrame in RX-TX link module.
  • The design negotiates the FRL rate between the sink connected to TX and the source connected to RX. The design passes through the EDID from the external sink to the on-board RX in default configuration. The Nios® II processor negotiates the link base on the capability of the sink connected to TX. You can also toggle the user_dipsw on-board switch to manually control the TX and RX FRL capabilities.
  • The design includes several debugging features.

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