HDMI Intel® Stratix 10 FPGA IP Design Example User Guide

ID 683701
Date 12/27/2022

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2.14. Design Limitations

You need to consider some limitations when instantiating the HDMI 2.1 design example.
  • TX is unable to operate in TMDS mode when in non-passthrough mode. To test in TMDS mode, toggle the user_dipsw switch back to passthrough mode.
  • The Nios® II processor must serve the TX link training to completion without any interruption from other processes.
  • Image may not display properly on the television or monitor on certain resolutions. To reset the display, press the CPU_Resetn button.
  • HDMI RX may not be able to lock when running at 16 bpc.