HDMI Intel® Stratix® 10 FPGA IP Design Example User Guide
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3.7. Design RTL Parameters
Most of the design parameters are available in the Design Example tab of the HDMI Intel® FPGA IP parameter editor. You can still change the design example settings you made in the parameter editor through the RTL parameters.
Parameter | Value | Description |
---|---|---|
SUPPORT_DEEP_COLOR |
|
Determines if the core can encode deep color formats. |
SUPPORT_AUXILIARY |
|
Determines if the auxiliary channel encoding is included. |
SYMBOLS_PER_CLOCK | 8 | Supports 8 symbols per clock for Intel® Stratix® 10 devices. |
SUPPORT_AUDIO |
|
Determines if the core can encode audio. |
EDID_RAM_ADDR_WIDTH | 8 (Default value) | Log base 2 of the EDID RAM size. |
Parameter | Value | Description |
---|---|---|
USE_FPLL | 1 | Supports fPLL as TX PLL only for Intel® Stratix® 10 devices. Always set this parameter to 1. |
SUPPORT_DEEP_COLOR |
|
Determines if the core can encode deep color formats. |
SUPPORT_AUXILIARY |
|
Determines if the auxiliary channel encoding is included. |
SYMBOLS_PER_CLOCK | 8 | Supports 8 symbols per clock for Intel® Stratix® 10 devices. |
SUPPORT_AUDIO |
|
Determines if the core can encode audio. |