||Added a new parameter for selecting HDMI daughter card revision to the Hardware and Software Requirements section of the design example quick start guide.
||Edited Disabling HDR Insertion and Filtering chapter to incorporate steps to disable HDR InfoFrame insertion and filtering for TMDS mode design.
- Notification of removal of Cygwin component from the Windows* version of Nios II EDS and the requirement to install WSL for Windows* users.
- Updated daughter card version from Revision 4 to 9 where applicable throughout the document.
- Replaced AN556 to Intel Stratix 10 Device Security User Guide in Protection of Encryption Key Embedded in FPGA Design.
- Updated the subsection Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) to describe the new key encryption software utility (KEYENC).
- Removed the following figures:
- Data array of Facsimile Key R1 for RX Private Key
- Data arrays of HDCP Production Keys (Placeholder)
- Data array of HDCP Protection Key (Predefined key)
- HDCP protection key initialized in hdcp2x_tx_kmem.mif
- HDCP protection key initialized in hdcp1x_rx_kmem.mif
- HDCP protection key initialized in hdcp1x_tx_kmem.mif
||Removed references to ncsim
- Added SUPPORT_HDCP_KEY_MANAGE = 1 to the description for Figure 29 HDCP Over HDMI Design Example Block Diagram.
- Added the steps in HDCP key memory files in Design Walkthrough.
- Added the step to turn on Support HDCP Key Management parameter in Generate the Design.
- Added a new subsection Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1).
- Added a new chapter Protection of Encryption Key Embedded in FPGA Design.
- Added a new chapter Debug Guidelines and subsection HDCP Status Signals, Modifying HDCP Software Parameter and Frequently Asked Questions.
- Updated Figure Components Required for RX-Only or TX-Only Design.
- Updated Table Generated RTL Files.
- Updated Figure HDMI RX Top Components.
- Removed Section HDMI RX Top Link Training Process.
- Updated the steps in Running the Design in Different FRL Rates.
- Updated Figure HDMI 2.1 Design Example Clocking Scheme.
- Updated Table Clocking Scheme Signals.
- Updated Figure HDMI RX-TX Block Diagram to add a connection from Transceiver Arbiter to TX top.
- Updated the HDMI Intel FPGA IP Design Example Quick Start Guide for Intel® Stratix® 10 Devices section with information about the newly added HDMI 2.1 design example with FRL mode.
- Added a new chapter, Detailed Description for HDMI 2.1 Design Example (Support FRL Enabled) that contains all the relevant information about the newly added design example.
- Updated the HDCP Over HDMI 2.0 Design Example section:
- Updated topic title HDCP Over HDMI 2.0 Design Example to HDCP Over HDMI 2.0/2.1 Design Example
- Added new hardware setup when SUPPORT_FRL = 1 in the Set Up the Hardware section.
- Edited the Include HDCP Production Keys section to updated the design example top level file to <Intel Quartus Prime project name>.v
- Edited the Compile the Design section to update the .qpf file to <projectdirectory /quartus/<Intel Quartus Prime project name>.qpf
- Updated table name Push Button and LED Indicators to Push Button and LED Indicators (SUPPORT_FRL = 0).
- Added a new Table: Push Button and LED Indicators (SUPPORT_FRL =1).
- Updated the directory structure for Intel® Stratix® 10 design example and the generated files list in the Directory Structure section.
- Updated the block diagrams in the HDMI 2.0 RX-TX Retransmit Design Block Diagram, Generating TX or RX Only Designs, and Clocking Scheme sections.
- Updated the description for the RX and TX core components and removed the description for the PIO and I2C Master (TX) components from the Design Components section.
- Updated the description for the transceiver clock signals in the Clocking Scheme section.
- Added RX CDR reference clock information in the Clocking Scheme section.
- Removed irrelevant signals, and added or edited the description of the following HDMI design example signals in the Interface Signals section:
- rx_pma* signals
- Added the EDID_RAM_ADDR_WIDTH parameter in the Design RTL Parameters section.
- Added a note that the simulation testbench is not supported for designs with the Include I2C parameter enabled and updated the simulation message in the Simulation Testbench section.
- Updated the Upgrading Your Design section.
- Added the build_sw_hdcp.sh script and removed the runall.tcl script from the Directory Structure section. The runall.tcl script is applicable only for the Intel® Quartus® Prime Standard Edition software.
- Added a list of HDMI Intel® FPGA IP design examples offered for Intel® Stratix® 10 devices in the HDMI Intel® FPGA IP Design Example Quick Start Guide section.
- Added a new section about the HDCP design example: HDCP Over HDMI 2.0 Design Examples. The HDCP feature is now available for Intel® Stratix® 10 devices.
- Updated the Directory Structure section to remove information about the i2c_master folder and the related files; and added the following files:
- Updated the Generating the Design section to change the part number for the Intel® Stratix® 10 device to 1SG280LU2F50E2V and 1SG280HU2F50E2VG. The design example targets the Intel® Stratix® 10 production device now.
- Edited the Hardware and Software Requirements section to include Intel® Stratix® 10 L-tile and update the Bitec HDMI FMC 2.0 daughter card to revision 11.
- Updated the HDMI Intel® FPGA IP Design Example Parameters section to include new options for the Select Board parameter. You can choose to use either the Stratix 10 GX FPGA H-tile or L-tile development kit for your Intel® Stratix® 10 designs.
- Added the following I2C and Hot Plug Detect signals in the Interface Signals section:
- Removed the following I2C and Hot Plug Detect signals in the Interface Signals section:
- Added the following Platform Designer signals in the Interface Signals section:
- Removed the following Platform Designer signals in the Interface Signals section:
- oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_address
- oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_write
- oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_readdata
- oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_writedata
- oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_waitrequest
- oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_chipselect
- Updated the description for fmcb_dp_m2c_p and fmcb_dp_c2m_p signals to add transceiver serial data mapping to the HDMI channels.
- Updated the Design RTL Parameters section to add information that the default Bitec HDMI FMC 2.0 daughter card is revision 11.
- Added Upgrading Your Design section to provide guidelines about upgrading your existing design to the latest version.