HDMI Intel® Stratix 10 FPGA IP Design Example User Guide

ID 683701
Date 12/27/2022

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4.3.2. Generate the Design

After setting up the hardware, you need to generate the design.
Before you begin, ensure to install the HDCP feature in the Intel® Quartus® Prime Pro Edition software.
  1. Click Tools > IP Catalog, and select Intel® Stratix® 10 as the target device family.
    Note: The HDCP design example supports only Intel® Arria® 10 and Intel® Stratix® 10 devices.
  2. In the IP Catalog, locate and double-click HDMI Intel® FPGA IP. The New IP variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.qsys or <your_ip>.ip.
  4. Click OK. The parameter editor appears.
  5. On the IP tab, configure the desired parameters for both TX and RX.
  6. Turn on the Support HDCP 1.4 or Support HDCP 2.3 parameter to generate the HDCP design example.
  7. Turn on the Support HDCP Key Management parameter if you want to store the HDCP production key in an encrypted format in the external flash memory or EEPROM. Otherwise, turn off the Support HDCP Key Management parameter to store the HDCP production key in plain format in the FPGA.
  8. On the Design Example tab, select Stratix 10 HDMI RX-TX Retransmit.
  9. Select Synthesis to generate the hardware design example.
  10. For Generate File Format, select Verilog or VHDL.
  11. For Select Board, select the relevant development kit. You may change the target device using the Change Target Device parameter if your board revision does not match the grade of the default targeted device. For Stratix 10 GX FPGA L-tile Development Kit, the default device is 1SG280LU2F50E2VG, and for Stratix 10 GX FPGA H-tile Development Kit, the default device is 1SG280HU2F50E2VG.
  12. Click Generate Example Design to generate the project files and the software Executable and Linking Format (ELF) programming file.