4.6. Arria® 10 EPE - Clock Worksheet
Arria® 10 devices support global, regional, and periphery clock networks. The EPE spreadsheet does not distinguish between global or regional clocks because the difference in power is not significant.
|Domain||Specify a name for the clock domain in this row. This is an optional value.|
|Clock Freq (MHz)||Enter the frequency of the clock domain. This value is limited by the maximum frequency specification for the device family.
Note: When you import a design from the Quartus Prime software, some imported clocks may have a frequency of 0 MHz, due to either of the following reasons:
Enter the total number of flipflops, RAMs, digital signal processing (DSP) blocks, and I/O pins fed by this clock.
Power consumed by MLAB clocks is accounted for in the RAM worksheet; therefore, clock fanout on this worksheet does not include any MLABs driven by this clock domain.
The number of resources driven by every global clock and regional clock signal is reported in the Fan-out column of the Quartus® Prime Compilation Report. In the Compilation Report, select Fitter and click Resources Section. Select Global & Other Fast Signals Summary and observe the Fan-out value.
|Global Enable %||Enter the average percentage of time that the entire clock tree is enabled. Each global clock buffer has an enable signal that you can use to dynamically shut down the entire clock tree.|
|Local Enable %||
Enter the average percentage of time that clock enable is high for destination flipflops.
Local clock enables for flipflops in ALMs are promoted to LAB-wide signals. When a given flipflop is disabled, the LAB-wide clock is disabled, cutting clock power and the power for down-stream logic. This worksheet models only the impact on clock tree power.
Represents the impact of the clock network configuration on power.
Characteristics that have a large impact on power and are captured by this factor include the following:
The default value for this field is typical; the actual value varies between clocks in your design, and depends on the placement of your design. For most accurate results, you should import this value from the Quartus Prime software, because the Quartus Prime software has access to detailed placement information.
In the absence of a Quartus Prime design, higher values generally correspond to signals that span large distances on the FPGA and fanout to many destinations, while lower values correspond to more localized signals.
You can change this field from its default value to explore possible variations in power consumption depending on block placement. When changing this value, keep in mind that typical designs rarely use extreme values, and only for a small subset of the design.
|Total Power (W)||Indicates the total power dissipation due to clock distribution (in W).|
|User Comments||Enter any comments. This is an optional entry.|
For more information about the clock networks of Arria® 10 devices, refer to the Clock Networks and PLLs chapter of the Arria® 10 Device Handbook.
Did you find the information on this page useful?